miao.vhdl

来自「数字钟的实现」· VHDL 代码 · 共 49 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity miao is
    Port ( CLK : in std_logic;
           CLR:  in std_logic;
		 ZANTING: in std_logic;
		 COUT: out std_logic;
           SECSHI,SECGE : out std_logic_vector(3 downto 0));
end miao;

architecture Behavioral of miao is
begin
 process (CLR,ZANTING,CLK)
  VARIABLE CNT1,CNT0:STD_LOGIC_VECTOR(3 DOWNTO 0); 
  begin
   IF CLR='1'THEN 
         CNT1:="0000";
	    CNT0:="0000";
   ELSIF ZANTING='1'THEN
	    CNT0:=CNT0;
   ELSIF CLK='1' AND  CLK'event THEN
      IF CNT1="0101" AND CNT0="1000" THEN
	    CNT0:="1001";
	    COUT<='1';
      ELSIF CNT0<"1001" THEN 
         CNT0:=CNT0+1;
	 ELSE    
	    CNT0:="0000";
	    IF CNT1<"0101" THEN
	       CNT1:=CNT1+1;
	    ELSE
	       CNT1:="0000";
		  COUT<='0';
      END IF;
    END IF;
  END IF;
        SECSHI<=CNT1;
	   SECGE<=CNT0;
end process;
end Behavioral;