📄 phase_reg.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 6/ 96( 6%) 5/ 48( 10%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 5/ 96( 5%) 0/ 48( 0%) 5/ 48( 10%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\phase_reg.rpt
phase_reg
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 15 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\phase_reg.rpt
phase_reg
** EQUATIONS **
clk : INPUT;
Datain0 : INPUT;
Datain1 : INPUT;
Datain2 : INPUT;
Datain3 : INPUT;
Datain4 : INPUT;
Datain5 : INPUT;
Datain6 : INPUT;
Datain7 : INPUT;
Datain8 : INPUT;
Datain9 : INPUT;
Datain10 : INPUT;
Datain11 : INPUT;
Datain12 : INPUT;
Datain13 : INPUT;
Datain14 : INPUT;
reset : INPUT;
-- Node name is ':47' = 'buff0'
-- Equation name is 'buff0', location is LC1_C19, type is buried.
buff0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = Datain0 & !reset;
-- Node name is ':46' = 'buff1'
-- Equation name is 'buff1', location is LC6_B11, type is buried.
buff1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = Datain1 & !reset;
-- Node name is ':45' = 'buff2'
-- Equation name is 'buff2', location is LC2_B11, type is buried.
buff2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = Datain2 & !reset;
-- Node name is ':44' = 'buff3'
-- Equation name is 'buff3', location is LC6_C19, type is buried.
buff3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = Datain3 & !reset;
-- Node name is ':43' = 'buff4'
-- Equation name is 'buff4', location is LC3_C19, type is buried.
buff4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = Datain4 & !reset;
-- Node name is ':42' = 'buff5'
-- Equation name is 'buff5', location is LC5_C19, type is buried.
buff5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = Datain5 & !reset;
-- Node name is ':41' = 'buff6'
-- Equation name is 'buff6', location is LC3_B11, type is buried.
buff6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = Datain6 & !reset;
-- Node name is ':40' = 'buff7'
-- Equation name is 'buff7', location is LC4_C19, type is buried.
buff7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = Datain7 & !reset;
-- Node name is ':39' = 'buff8'
-- Equation name is 'buff8', location is LC4_B11, type is buried.
buff8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = Datain8 & !reset;
-- Node name is ':38' = 'buff9'
-- Equation name is 'buff9', location is LC5_B11, type is buried.
buff9 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = Datain9 & !reset;
-- Node name is ':37' = 'buff10'
-- Equation name is 'buff10', location is LC7_C19, type is buried.
buff10 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = Datain10 & !reset;
-- Node name is ':36' = 'buff11'
-- Equation name is 'buff11', location is LC8_B11, type is buried.
buff11 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = Datain11 & !reset;
-- Node name is ':35' = 'buff12'
-- Equation name is 'buff12', location is LC2_C19, type is buried.
buff12 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = Datain12 & !reset;
-- Node name is ':34' = 'buff13'
-- Equation name is 'buff13', location is LC1_B11, type is buried.
buff13 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = Datain13 & !reset;
-- Node name is ':33' = 'buff14'
-- Equation name is 'buff14', location is LC7_B11, type is buried.
buff14 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = Datain14 & !reset;
-- Node name is 'Dataout0'
-- Equation name is 'Dataout0', type is output
Dataout0 = buff0;
-- Node name is 'Dataout1'
-- Equation name is 'Dataout1', type is output
Dataout1 = buff1;
-- Node name is 'Dataout2'
-- Equation name is 'Dataout2', type is output
Dataout2 = buff2;
-- Node name is 'Dataout3'
-- Equation name is 'Dataout3', type is output
Dataout3 = buff3;
-- Node name is 'Dataout4'
-- Equation name is 'Dataout4', type is output
Dataout4 = buff4;
-- Node name is 'Dataout5'
-- Equation name is 'Dataout5', type is output
Dataout5 = buff5;
-- Node name is 'Dataout6'
-- Equation name is 'Dataout6', type is output
Dataout6 = buff6;
-- Node name is 'Dataout7'
-- Equation name is 'Dataout7', type is output
Dataout7 = buff7;
-- Node name is 'Dataout8'
-- Equation name is 'Dataout8', type is output
Dataout8 = buff8;
-- Node name is 'Dataout9'
-- Equation name is 'Dataout9', type is output
Dataout9 = buff9;
-- Node name is 'Dataout10'
-- Equation name is 'Dataout10', type is output
Dataout10 = buff10;
-- Node name is 'Dataout11'
-- Equation name is 'Dataout11', type is output
Dataout11 = buff11;
-- Node name is 'Dataout12'
-- Equation name is 'Dataout12', type is output
Dataout12 = buff12;
-- Node name is 'Dataout13'
-- Equation name is 'Dataout13', type is output
Dataout13 = buff13;
-- Node name is 'Dataout14'
-- Equation name is 'Dataout14', type is output
Dataout14 = buff14;
Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\phase_reg.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,815K
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