kdtest1.rpt

这是用VHDL语言编写的一个DDS频率合成器的源程序

-- Node name is '|KEY_DECODER:1|:16' 
-- Equation name is '_LC5_B23', type is buried 
_LC5_B23 = DFFE( _EQ007,  clk,  VCC,  VCC,  VCC);
  _EQ007 = !_LC6_B17 & !_LC8_B17
         # !_LC2_B18 & !_LC6_B17
         # !_LC2_B23;

-- Node name is '|KEY_DECODER:1|:18' 
-- Equation name is '_LC3_B23', type is buried 
_LC3_B23 = DFFE( _EQ008,  clk,  VCC,  VCC,  VCC);
  _EQ008 =  _LC2_B23
         #  _LC2_B18 &  _LC4_B17;

-- Node name is '|KEY_DECODER:1|:20' 
-- Equation name is '_LC1_B17', type is buried 
_LC1_B17 = DFFE( _EQ009,  clk,  VCC,  VCC,  VCC);
  _EQ009 =  _LC4_B23
         # !_LC4_B17 &  _LC6_B17
         # !_LC2_B17 & !_LC4_B17;

-- Node name is '|KEY_DECODER:1|:22' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = DFFE( _EQ010,  clk,  VCC,  VCC,  VCC);
  _EQ010 =  _LC2_B18 &  _LC4_B17
         #  _LC2_B18 &  _LC6_B17
         #  _LC1_B18 & !_LC4_B17 & !_LC6_B17;

-- Node name is '|KEY_DECODER:1|~204~1' 
-- Equation name is '_LC4_C23', type is buried 
-- synthesized logic cell 
_LC4_C23 = LCELL( _EQ011);
  _EQ011 =  ki0 &  ki1;

-- Node name is '|KEY_DECODER:1|:216' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ012);
  _EQ012 =  ki0 &  ki1 & !ki2 &  ki3;

-- Node name is '|KEY_DECODER:1|:240' 
-- Equation name is '_LC8_C23', type is buried 
!_LC8_C23 = _LC8_C23~NOT;
_LC8_C23~NOT = LCELL( _EQ013);
  _EQ013 = !ki2
         # !ki3
         #  ki0
         # !ki1;

-- Node name is '|KEY_DECODER:1|~719~1' 
-- Equation name is '_LC2_C23', type is buried 
-- synthesized logic cell 
!_LC2_C23 = _LC2_C23~NOT;
_LC2_C23~NOT = LCELL( _EQ014);
  _EQ014 =  _LC3_C23
         #  ki2 & !ki3 &  _LC4_C23;

-- Node name is '|KEY_DECODER:1|:719' 
-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = LCELL( _EQ015);
  _EQ015 = !_LC1_C23
         # !_LC2_C23;

-- Node name is '|KEY_DECODER:1|:1108' 
-- Equation name is '_LC5_B17', type is buried 
_LC5_B17 = LCELL( _EQ016);
  _EQ016 =  _LC1_B17 &  _LC3_B23 &  _LC5_B23 & !_LC7_B17;

-- Node name is '|KEY_DECODER:1|:1120' 
-- Equation name is '_LC8_B17', type is buried 
_LC8_B17 = LCELL( _EQ017);
  _EQ017 =  _LC1_B17 &  _LC3_B23 & !_LC5_B23 &  _LC7_B17;

-- Node name is '|KEY_DECODER:1|:1124' 
-- Equation name is '_LC3_B17', type is buried 
_LC3_B17 = LCELL( _EQ018);
  _EQ018 =  _LC2_B18 &  _LC8_B17;

-- Node name is '|KEY_DECODER:1|:1125' 
-- Equation name is '_LC2_B17', type is buried 
!_LC2_B17 = _LC2_B17~NOT;
_LC2_B17~NOT = LCELL( _EQ019);
  _EQ019 =  _LC8_B17
         #  _LC2_B18 &  _LC5_B17;

-- Node name is '|KEY_DECODER:1|:1132' 
-- Equation name is '_LC6_B17', type is buried 
_LC6_B17 = LCELL( _EQ020);
  _EQ020 =  _LC1_B17 & !_LC3_B23 &  _LC5_B23 &  _LC7_B17;

-- Node name is '|KEY_DECODER:1|:1144' 
-- Equation name is '_LC4_B17', type is buried 
!_LC4_B17 = _LC4_B17~NOT;
_LC4_B17~NOT = LCELL( _EQ021);
  _EQ021 = !_LC7_B17
         # !_LC5_B23
         # !_LC3_B23
         #  _LC1_B17;

-- Node name is '|KEY_DECODER:1|:1179' 
-- Equation name is '_LC2_B23', type is buried 
_LC2_B23 = LCELL( _EQ022);
  _EQ022 = !_LC4_B17 & !_LC6_B17
         # !_LC2_B18 & !_LC4_B17;

-- Node name is '|KEY_DECODER:1|:1193' 
-- Equation name is '_LC4_B23', type is buried 
_LC4_B23 = LCELL( _EQ023);
  _EQ023 = !_LC2_B18 &  _LC4_B17;

-- Node name is '|KEY_DECODER:1|~1208~1' 
-- Equation name is '_LC1_C23', type is buried 
-- synthesized logic cell 
!_LC1_C23 = _LC1_C23~NOT;
_LC1_C23~NOT = LCELL( _EQ024);
  _EQ024 =  ki0 & !ki1 &  ki2 &  ki3
         # !ki0 &  ki1 &  ki2 &  ki3;

-- Node name is '|KEY_DECODER:1|~1222~1' 
-- Equation name is '_LC6_C23', type is buried 
-- synthesized logic cell 
_LC6_C23 = LCELL( _EQ025);
  _EQ025 =  ki0 & !ki1 &  ki2 &  ki3
         #  ki0 &  ki1 &  ki2 & !ki3;

-- Node name is '|KEY_DECODER:1|~1222~2' 
-- Equation name is '_LC7_B18', type is buried 
-- synthesized logic cell 
!_LC7_B18 = _LC7_B18~NOT;
_LC7_B18~NOT = LCELL( _EQ026);
  _EQ026 = !_LC4_B17 & !_LC5_B17 & !_LC6_B17 & !_LC8_B17;

-- Node name is '|KEY_DECODER:1|~1222~3' 
-- Equation name is '_LC7_C23', type is buried 
-- synthesized logic cell 
_LC7_C23 = LCELL( _EQ027);
  _EQ027 =  _LC6_C23 &  _LC7_B18
         # !_LC3_C23 &  _LC5_C23;

-- Node name is '|KEY_DECODER:1|~1237~1' 
-- Equation name is '_LC7_B23', type is buried 
-- synthesized logic cell 
_LC7_B23 = LCELL( _EQ028);
  _EQ028 =  _LC2_B18 &  _LC8_B17
         #  _LC2_B18 &  _LC5_B17;

-- Node name is '|KEY_DECODER:1|~1252~1' 
-- Equation name is '_LC6_B18', type is buried 
-- synthesized logic cell 
_LC6_B18 = LCELL( _EQ029);
  _EQ029 =  _LC5_B17 & !_LC8_B17
         #  _LC6_B17;

-- Node name is '|KEY_DECODER:1|~1252~2' 
-- Equation name is '_LC6_B23', type is buried 
-- synthesized logic cell 
_LC6_B23 = LCELL( _EQ030);
  _EQ030 =  _LC1_B23 & !_LC8_B17
         #  _LC1_B23 & !_LC2_B18
         #  _LC2_B18 &  _LC6_B18;

-- Node name is '|KEY_DECODER:1|:1261' 
-- Equation name is '_LC1_B18', type is buried 
_LC1_B18 = LCELL( _EQ031);
  _EQ031 =  _LC2_B18 &  _LC8_B17
         #  _LC2_B18 &  _LC5_B17;



Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\kdtest1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,276K