📄 kdtest1.rpt
字号:
81 - - - 22 OUTPUT 0 0 0 0 data4
83 - - - 13 OUTPUT 0 0 0 0 data5
3 - - - 12 OUTPUT 0 0 0 0 data6
5 - - - 05 OUTPUT 0 0 0 0 data7
17 - - A -- OUTPUT 0 1 0 0 int
67 - - B -- OUTPUT 0 1 0 0 ko0
66 - - B -- OUTPUT 0 1 0 0 ko1
65 - - B -- OUTPUT 0 1 0 0 ko2
64 - - B -- OUTPUT 0 1 0 0 ko3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\kdtest1.rpt
kdtest1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 18 DFFE 1 1 0 2 |ANTISHAKE1:2|s1 (|ANTISHAKE1:2|:4)
- 8 - B 18 DFFE 1 1 0 1 |ANTISHAKE1:2|s2 (|ANTISHAKE1:2|:5)
- 3 - B 18 OR2 ! 0 2 1 0 |ANTISHAKE1:2|:36
- 2 - C 24 DFFE 1 3 1 0 |KEY_DECODER:1|:6
- 5 - C 23 DFFE 1 3 1 1 |KEY_DECODER:1|:8
- 8 - B 23 DFFE 1 3 1 0 |KEY_DECODER:1|:10
- 1 - B 23 DFFE 1 3 1 1 |KEY_DECODER:1|:12
- 7 - B 17 DFFE 1 4 1 4 |KEY_DECODER:1|:14
- 5 - B 23 DFFE 1 4 1 4 |KEY_DECODER:1|:16
- 3 - B 23 DFFE 1 3 1 4 |KEY_DECODER:1|:18
- 1 - B 17 DFFE 1 4 1 4 |KEY_DECODER:1|:20
- 4 - B 18 DFFE 1 4 0 1 |KEY_DECODER:1|:22
- 4 - C 23 AND2 s 0 2 0 1 |KEY_DECODER:1|~204~1
- 3 - C 23 AND2 0 4 0 2 |KEY_DECODER:1|:216
- 8 - C 23 OR2 ! 0 4 0 1 |KEY_DECODER:1|:240
- 2 - C 23 OR2 s ! 0 4 0 2 |KEY_DECODER:1|~719~1
- 2 - B 18 OR2 0 2 0 10 |KEY_DECODER:1|:719
- 5 - B 17 AND2 0 4 0 5 |KEY_DECODER:1|:1108
- 8 - B 17 AND2 0 4 0 8 |KEY_DECODER:1|:1120
- 3 - B 17 AND2 0 2 0 1 |KEY_DECODER:1|:1124
- 2 - B 17 OR2 ! 0 3 0 2 |KEY_DECODER:1|:1125
- 6 - B 17 AND2 0 4 0 7 |KEY_DECODER:1|:1132
- 4 - B 17 OR2 ! 0 4 0 8 |KEY_DECODER:1|:1144
- 2 - B 23 OR2 0 3 0 3 |KEY_DECODER:1|:1179
- 4 - B 23 AND2 0 2 0 3 |KEY_DECODER:1|:1193
- 1 - C 23 OR2 s ! 0 4 0 2 |KEY_DECODER:1|~1208~1
- 6 - C 23 OR2 s 0 4 0 1 |KEY_DECODER:1|~1222~1
- 7 - B 18 AND2 s ! 0 4 0 3 |KEY_DECODER:1|~1222~2
- 7 - C 23 OR2 s 0 4 0 1 |KEY_DECODER:1|~1222~3
- 7 - B 23 OR2 s 0 3 0 1 |KEY_DECODER:1|~1237~1
- 6 - B 18 OR2 s 0 3 0 1 |KEY_DECODER:1|~1252~1
- 6 - B 23 OR2 s 0 4 0 1 |KEY_DECODER:1|~1252~2
- 1 - B 18 OR2 0 3 0 1 |KEY_DECODER:1|:1261
- 4 - C 24 DFFE 2 0 0 5 ki3 (:11)
- 5 - C 24 DFFE 2 0 0 5 ki2 (:12)
- 6 - C 24 DFFE 2 0 0 5 ki1 (:13)
- 3 - C 24 DFFE 2 0 0 5 ki0 (:14)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\kdtest1.rpt
kdtest1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 0/ 48( 0%) 1/ 48( 2%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 13/ 48( 27%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 8/ 48( 16%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\kdtest1.rpt
kdtest1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 15 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\kdtest1.rpt
kdtest1
** EQUATIONS **
clk : INPUT;
key0 : INPUT;
key1 : INPUT;
key2 : INPUT;
key3 : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC1_B23;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC8_B23;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC5_C23;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC2_C24;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = GND;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = GND;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = GND;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = GND;
-- Node name is 'int'
-- Equation name is 'int', type is output
int = !_LC3_B18;
-- Node name is ':14' = 'ki0'
-- Equation name is 'ki0', location is LC3_C24, type is buried.
ki0 = DFFE( key0, !clk, VCC, VCC, VCC);
-- Node name is ':13' = 'ki1'
-- Equation name is 'ki1', location is LC6_C24, type is buried.
ki1 = DFFE( key1, !clk, VCC, VCC, VCC);
-- Node name is ':12' = 'ki2'
-- Equation name is 'ki2', location is LC5_C24, type is buried.
ki2 = DFFE( key2, !clk, VCC, VCC, VCC);
-- Node name is ':11' = 'ki3'
-- Equation name is 'ki3', location is LC4_C24, type is buried.
ki3 = DFFE( key3, !clk, VCC, VCC, VCC);
-- Node name is 'ko0'
-- Equation name is 'ko0', type is output
ko0 = _LC1_B17;
-- Node name is 'ko1'
-- Equation name is 'ko1', type is output
ko1 = _LC3_B23;
-- Node name is 'ko2'
-- Equation name is 'ko2', type is output
ko2 = _LC5_B23;
-- Node name is 'ko3'
-- Equation name is 'ko3', type is output
ko3 = _LC7_B17;
-- Node name is '|ANTISHAKE1:2|:4' = '|ANTISHAKE1:2|s1'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = DFFE( _LC4_B18, !clk, VCC, VCC, VCC);
-- Node name is '|ANTISHAKE1:2|:5' = '|ANTISHAKE1:2|s2'
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = DFFE( _LC5_B18, !clk, VCC, VCC, VCC);
-- Node name is '|ANTISHAKE1:2|:36'
-- Equation name is '_LC3_B18', type is buried
!_LC3_B18 = _LC3_B18~NOT;
_LC3_B18~NOT = LCELL( _EQ001);
_EQ001 = _LC8_B18
# !_LC5_B18;
-- Node name is '|KEY_DECODER:1|:6'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = _LC2_C24 & !_LC7_B18
# _LC1_C23 & _LC2_C24
# _LC1_C23 & !_LC2_C23 & _LC7_B18;
-- Node name is '|KEY_DECODER:1|:8'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = _LC7_C23 & !_LC8_C23
# _LC5_C23 & !_LC7_B18;
-- Node name is '|KEY_DECODER:1|:10'
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = DFFE( _EQ004, clk, VCC, VCC, VCC);
_EQ004 = _LC4_B23 & _LC8_B23
# _LC2_B23 & _LC8_B23
# _LC2_B23 & _LC7_B23;
-- Node name is '|KEY_DECODER:1|:12'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = DFFE( _EQ005, clk, VCC, VCC, VCC);
_EQ005 = _LC1_B23 & _LC4_B23
# !_LC4_B17 & _LC6_B23;
-- Node name is '|KEY_DECODER:1|:14'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = DFFE( _EQ006, clk, VCC, VCC, VCC);
_EQ006 = _LC3_B17
# _LC6_B17
# _LC4_B17
# _LC2_B17;
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