phase_adder.vhd

这是用VHDL语言编写的一个DDS频率合成器的源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity phase_adder is
port
(
	clk	:	in std_logic;
	M	:	in std_logic_vector (15 downto 0);
	Prev_Phase	:in std_logic_vector (16 downto 0);
	reset	:	in std_logic;
	Current_Phase	:out std_logic_vector (16 downto 0)
	--WE		:out std_logic
);
end phase_adder;
architecture behave of phase_adder is
begin
	process(clk)
	begin
		if (clk'event and clk='1') then
			--WE<='0';
			if (reset='1') then Current_Phase<="00000000000000000";
			else Current_Phase<=Prev_Phase+('0'& M);
			end if;
		
		end if;
		
	end process;
end behave;