📄 scandiv.rpt
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09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\scandiv.rpt
scandiv
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\scandiv.rpt
scandiv
** EQUATIONS **
clk : INPUT;
-- Node name is 'clk_out'
-- Equation name is 'clk_out', type is output
clk_out = _LC7_B17;
-- Node name is ':19' = 'num0'
-- Equation name is 'num0', location is LC3_B19, type is buried.
num0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC2_B19 & !num0;
-- Node name is ':18' = 'num1'
-- Equation name is 'num1', location is LC4_B19, type is buried.
num1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC2_B19 & num0 & !num1
# !_LC2_B19 & !num0 & num1;
-- Node name is ':17' = 'num2'
-- Equation name is 'num2', location is LC5_B19, type is buried.
num2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC2_B19 & !num0 & num2
# !_LC2_B19 & !num1 & num2
# !_LC2_B19 & num0 & num1 & !num2;
-- Node name is ':16' = 'num3'
-- Equation name is 'num3', location is LC2_B17, type is buried.
num3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_B19 & !_LC2_B19 & num3
# _LC1_B19 & !_LC2_B19 & !num3;
-- Node name is ':15' = 'num4'
-- Equation name is 'num4', location is LC5_B17, type is buried.
num4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC2_B19 & !num3 & num4
# !_LC1_B19 & !_LC2_B19 & num4
# _LC1_B19 & !_LC2_B19 & num3 & !num4;
-- Node name is ':14' = 'num5'
-- Equation name is 'num5', location is LC6_B17, type is buried.
num5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC2_B19 & !_LC3_B17 & num5
# !_LC2_B19 & _LC3_B17 & !num5;
-- Node name is ':13' = 'num6'
-- Equation name is 'num6', location is LC8_B17, type is buried.
num6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC2_B19 & !num5 & num6
# !_LC2_B19 & !_LC3_B17 & num6
# !_LC2_B19 & _LC3_B17 & num5 & !num6;
-- Node name is ':12' = 'num7'
-- Equation name is 'num7', location is LC1_B20, type is buried.
num7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC2_B19 & !_LC4_B17 & num7
# !_LC2_B19 & _LC4_B17 & !num7;
-- Node name is ':11' = 'num8'
-- Equation name is 'num8', location is LC6_B20, type is buried.
num8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC2_B19 & !num7 & num8
# !_LC2_B19 & !_LC4_B17 & num8
# !_LC2_B19 & _LC4_B17 & num7 & !num8;
-- Node name is ':10' = 'num9'
-- Equation name is 'num9', location is LC7_B20, type is buried.
num9 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !_LC2_B19 & !_LC5_B20 & num9
# !_LC2_B19 & _LC5_B20 & !num9;
-- Node name is ':9' = 'num10'
-- Equation name is 'num10', location is LC8_B20, type is buried.
num10 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !_LC2_B19 & !num9 & num10
# !_LC2_B19 & !_LC5_B20 & num10
# !_LC2_B19 & _LC5_B20 & num9 & !num10;
-- Node name is ':8' = 'num11'
-- Equation name is 'num11', location is LC2_B22, type is buried.
num11 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !_LC2_B19 & !_LC4_B20 & num11
# !_LC2_B19 & _LC4_B20 & !num11;
-- Node name is ':7' = 'num12'
-- Equation name is 'num12', location is LC3_B22, type is buried.
num12 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !_LC2_B19 & !num11 & num12
# !_LC2_B19 & !_LC4_B20 & num12
# !_LC2_B19 & _LC4_B20 & num11 & !num12;
-- Node name is ':6' = 'num13'
-- Equation name is 'num13', location is LC5_B22, type is buried.
num13 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !_LC2_B19 & !_LC4_B22 & num13
# !_LC2_B19 & _LC4_B22 & !num13;
-- Node name is ':5' = 'num14'
-- Equation name is 'num14', location is LC6_B22, type is buried.
num14 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !_LC2_B19 & !num13 & num14
# !_LC2_B19 & !_LC4_B22 & num14
# !_LC2_B19 & _LC4_B22 & num13 & !num14;
-- Node name is ':4' = 'num15'
-- Equation name is 'num15', location is LC8_B22, type is buried.
num15 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !_LC2_B19 & !num14 & num15
# !_LC2_B19 & !_LC7_B22 & num15
# !_LC2_B19 & _LC7_B22 & num14 & !num15;
-- Node name is '|LPM_ADD_SUB:190|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B19', type is buried
_LC1_B19 = LCELL( _EQ017);
_EQ017 = num0 & num1 & num2;
-- Node name is '|LPM_ADD_SUB:190|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = LCELL( _EQ018);
_EQ018 = _LC1_B19 & num3 & num4;
-- Node name is '|LPM_ADD_SUB:190|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B17', type is buried
_LC4_B17 = LCELL( _EQ019);
_EQ019 = _LC3_B17 & num5 & num6;
-- Node name is '|LPM_ADD_SUB:190|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = LCELL( _EQ020);
_EQ020 = _LC4_B17 & num7 & num8;
-- Node name is '|LPM_ADD_SUB:190|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B20', type is buried
_LC4_B20 = LCELL( _EQ021);
_EQ021 = _LC5_B20 & num9 & num10;
-- Node name is '|LPM_ADD_SUB:190|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = LCELL( _EQ022);
_EQ022 = _LC4_B20 & num11 & num12;
-- Node name is '|LPM_ADD_SUB:190|addcore:adder|:151' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B22', type is buried
_LC7_B22 = LCELL( _EQ023);
_EQ023 = _LC4_B22 & num13;
-- Node name is ':2'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = DFFE( _EQ024, GLOBAL( clk), VCC, VCC, VCC);
_EQ024 = !_LC2_B19 & _LC7_B17
# _LC2_B19 & !_LC7_B17;
-- Node name is '~85~1'
-- Equation name is '~85~1', location is LC1_B22, type is buried.
-- synthesized logic cell
_LC1_B22 = LCELL( _EQ025);
_EQ025 = num12
# num13
# !num14
# num15;
-- Node name is '~85~2'
-- Equation name is '~85~2', location is LC3_B20, type is buried.
-- synthesized logic cell
_LC3_B20 = LCELL( _EQ026);
_EQ026 = !num8
# !num9
# num10
# !num11;
-- Node name is '~85~3'
-- Equation name is '~85~3', location is LC1_B17, type is buried.
-- synthesized logic cell
_LC1_B17 = LCELL( _EQ027);
_EQ027 = num4
# num5
# num6
# num7;
-- Node name is '~85~4'
-- Equation name is '~85~4', location is LC2_B20, type is buried.
-- synthesized logic cell
_LC2_B20 = LCELL( _EQ028);
_EQ028 = _LC1_B22
# _LC3_B20
# !num3
# _LC1_B17;
-- Node name is ':85'
-- Equation name is '_LC2_B19', type is buried
!_LC2_B19 = _LC2_B19~NOT;
_LC2_B19~NOT = LCELL( _EQ029);
_EQ029 = num0
# num1
# num2
# _LC2_B20;
Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\scandiv.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,429K
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