📄 testint.rpt
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Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\testint.rpt
testint
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\testint.rpt
testint
** EQUATIONS **
clk : INPUT;
-- Node name is 'int'
-- Equation name is 'int', type is output
int = _LC3_A23;
-- Node name is '|FREQDIV:3|LPM_ADD_SUB:179|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A19', type is buried
!_LC1_A19 = _LC1_A19~NOT;
_LC1_A19~NOT = LCELL( _EQ001);
_EQ001 = !_LC4_A19
# !_LC5_A19
# !_LC6_A19;
-- Node name is '|FREQDIV:3|LPM_ADD_SUB:179|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A19', type is buried
!_LC3_A19 = _LC3_A19~NOT;
_LC3_A19~NOT = LCELL( _EQ002);
_EQ002 = !_LC2_A17
# !_LC1_A19;
-- Node name is '|FREQDIV:3|LPM_ADD_SUB:179|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A19', type is buried
!_LC2_A19 = _LC2_A19~NOT;
_LC2_A19~NOT = LCELL( _EQ003);
_EQ003 = !_LC7_A19
# !_LC8_A19
# !_LC3_A19;
-- Node name is '|FREQDIV:3|LPM_ADD_SUB:179|addcore:adder|:119' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A14', type is buried
!_LC3_A14 = _LC3_A14~NOT;
_LC3_A14~NOT = LCELL( _EQ004);
_EQ004 = !_LC5_A14
# !_LC2_A19;
-- Node name is '|FREQDIV:3|LPM_ADD_SUB:179|addcore:adder|:127' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A14', type is buried
!_LC4_A14 = _LC4_A14~NOT;
_LC4_A14~NOT = LCELL( _EQ005);
_EQ005 = !_LC6_A14
# !_LC7_A14
# !_LC3_A14;
-- Node name is '|FREQDIV:3|LPM_ADD_SUB:179|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A14', type is buried
!_LC2_A14 = _LC2_A14~NOT;
_LC2_A14~NOT = LCELL( _EQ006);
_EQ006 = !_LC8_A14
# !_LC4_A14;
-- Node name is '|FREQDIV:3|LPM_ADD_SUB:179|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A23', type is buried
!_LC1_A23 = _LC1_A23~NOT;
_LC1_A23~NOT = LCELL( _EQ007);
_EQ007 = !_LC4_A23
# !_LC1_A14
# !_LC2_A14;
-- Node name is '|FREQDIV:3|LPM_ADD_SUB:179|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A23', type is buried
!_LC2_A23 = _LC2_A23~NOT;
_LC2_A23~NOT = LCELL( _EQ008);
_EQ008 = !_LC5_A23
# !_LC1_A23;
-- Node name is '|FREQDIV:3|:18' = '|FREQDIV:3|num0'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = DFFE(!_LC5_A19, clk, VCC, VCC, VCC);
-- Node name is '|FREQDIV:3|:17' = '|FREQDIV:3|num1'
-- Equation name is '_LC6_A19', type is buried
_LC6_A19 = DFFE( _EQ009, clk, VCC, VCC, VCC);
_EQ009 = _LC5_A19 & !_LC6_A19 & !_LC6_A23
# !_LC5_A19 & _LC6_A19 & !_LC6_A23;
-- Node name is '|FREQDIV:3|:16' = '|FREQDIV:3|num2'
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = DFFE( _EQ010, clk, VCC, VCC, VCC);
_EQ010 = _LC4_A19 & !_LC5_A19 & !_LC6_A23
# _LC4_A19 & !_LC6_A19 & !_LC6_A23
# !_LC4_A19 & _LC5_A19 & _LC6_A19 & !_LC6_A23;
-- Node name is '|FREQDIV:3|:15' = '|FREQDIV:3|num3'
-- Equation name is '_LC2_A17', type is buried
_LC2_A17 = DFFE( _EQ011, clk, VCC, VCC, VCC);
_EQ011 = !_LC1_A19 & _LC2_A17 & !_LC6_A23
# _LC1_A19 & !_LC2_A17 & !_LC6_A23;
-- Node name is '|FREQDIV:3|:14' = '|FREQDIV:3|num4'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = DFFE( _EQ012, clk, VCC, VCC, VCC);
_EQ012 = !_LC3_A19 & !_LC6_A23 & _LC8_A19
# _LC3_A19 & !_LC6_A23 & !_LC8_A19;
-- Node name is '|FREQDIV:3|:13' = '|FREQDIV:3|num5'
-- Equation name is '_LC7_A19', type is buried
_LC7_A19 = DFFE( _EQ013, clk, VCC, VCC, VCC);
_EQ013 = !_LC6_A23 & _LC7_A19 & !_LC8_A19
# !_LC3_A19 & !_LC6_A23 & _LC7_A19
# _LC3_A19 & !_LC6_A23 & !_LC7_A19 & _LC8_A19;
-- Node name is '|FREQDIV:3|:12' = '|FREQDIV:3|num6'
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = DFFE( _EQ014, clk, VCC, VCC, VCC);
_EQ014 = !_LC2_A19 & _LC5_A14 & !_LC6_A23
# _LC2_A19 & !_LC5_A14 & !_LC6_A23;
-- Node name is '|FREQDIV:3|:11' = '|FREQDIV:3|num7'
-- Equation name is '_LC7_A14', type is buried
_LC7_A14 = DFFE( _EQ015, clk, VCC, VCC, VCC);
_EQ015 = !_LC3_A14 & !_LC6_A23 & _LC7_A14
# _LC3_A14 & !_LC6_A23 & !_LC7_A14;
-- Node name is '|FREQDIV:3|:10' = '|FREQDIV:3|num8'
-- Equation name is '_LC6_A14', type is buried
_LC6_A14 = DFFE( _EQ016, clk, VCC, VCC, VCC);
_EQ016 = _LC6_A14 & !_LC6_A23 & !_LC7_A14
# !_LC3_A14 & _LC6_A14 & !_LC6_A23
# _LC3_A14 & !_LC6_A14 & !_LC6_A23 & _LC7_A14;
-- Node name is '|FREQDIV:3|:9' = '|FREQDIV:3|num9'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = DFFE( _EQ017, clk, VCC, VCC, VCC);
_EQ017 = !_LC4_A14 & !_LC6_A23 & _LC8_A14
# _LC4_A14 & !_LC6_A23 & !_LC8_A14;
-- Node name is '|FREQDIV:3|:8' = '|FREQDIV:3|num10'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = DFFE( _EQ018, clk, VCC, VCC, VCC);
_EQ018 = _LC1_A14 & !_LC2_A14 & !_LC6_A23
# !_LC1_A14 & _LC2_A14 & !_LC6_A23;
-- Node name is '|FREQDIV:3|:7' = '|FREQDIV:3|num11'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = DFFE( _EQ019, clk, VCC, VCC, VCC);
_EQ019 = !_LC1_A14 & _LC4_A23 & !_LC6_A23
# !_LC2_A14 & _LC4_A23 & !_LC6_A23
# _LC1_A14 & _LC2_A14 & !_LC4_A23 & !_LC6_A23;
-- Node name is '|FREQDIV:3|:6' = '|FREQDIV:3|num12'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = DFFE( _EQ020, clk, VCC, VCC, VCC);
_EQ020 = !_LC1_A23 & _LC5_A23 & !_LC6_A23
# _LC1_A23 & !_LC5_A23 & !_LC6_A23;
-- Node name is '|FREQDIV:3|:5' = '|FREQDIV:3|num13'
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = DFFE( _EQ021, clk, VCC, VCC, VCC);
_EQ021 = !_LC2_A23 & _LC7_A23
# _LC2_A23 & !_LC7_A23;
-- Node name is '|FREQDIV:3|:4' = '|FREQDIV:3|num14'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = DFFE( _EQ022, clk, VCC, VCC, VCC);
_EQ022 = !_LC7_A23 & _LC8_A23
# !_LC2_A23 & _LC8_A23
# _LC2_A23 & _LC7_A23 & !_LC8_A23;
-- Node name is '|FREQDIV:3|:2'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( _EQ023, clk, VCC, VCC, VCC);
_EQ023 = _LC3_A23 & !_LC7_A23
# !_LC2_A23 & _LC3_A23
# _LC3_A23 & !_LC8_A23
# _LC2_A23 & !_LC3_A23 & _LC7_A23 & _LC8_A23;
-- Node name is '|FREQDIV:3|:80'
-- Equation name is '_LC6_A23', type is buried
!_LC6_A23 = _LC6_A23~NOT;
_LC6_A23~NOT = LCELL( _EQ024);
_EQ024 = !_LC8_A23
# !_LC7_A23
# !_LC2_A23;
Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\testint.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,064K
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