📄 dds.rpt
字号:
- 1 - A 05 DFFE 1 3 1 0 |CONTROL1:1|:7
- 4 - A 12 DFFE 1 3 1 0 |CONTROL1:1|:9
- 1 - B 13 DFFE 1 3 1 0 |CONTROL1:1|:11
- 1 - B 22 DFFE 1 3 1 0 |CONTROL1:1|:13
- 6 - B 23 DFFE 1 4 1 1 |CONTROL1:1|:15
- 7 - B 23 DFFE 1 4 1 1 |CONTROL1:1|:17
- 8 - B 23 DFFE 1 4 1 1 |CONTROL1:1|:19
- 1 - A 12 DFFE 1 4 1 2 |CONTROL1:1|:21
- 1 - A 09 DFFE 1 2 0 2 |CONTROL1:1|:23
- 5 - A 16 DFFE 1 2 0 2 |CONTROL1:1|:25
- 5 - A 09 DFFE 1 3 0 2 |CONTROL1:1|:27
- 2 - A 04 DFFE 1 3 0 2 |CONTROL1:1|:29
- 3 - A 04 DFFE 1 3 0 2 |CONTROL1:1|:31
- 2 - A 01 DFFE 1 3 0 2 |CONTROL1:1|:33
- 1 - A 03 DFFE 1 3 0 2 |CONTROL1:1|:35
- 5 - A 03 DFFE 1 3 0 2 |CONTROL1:1|:37
- 2 - A 09 DFFE 1 3 0 2 |CONTROL1:1|:39
- 7 - A 06 DFFE 1 3 0 2 |CONTROL1:1|:41
- 8 - A 04 DFFE 1 3 0 2 |CONTROL1:1|:43
- 1 - A 06 DFFE 1 3 0 2 |CONTROL1:1|:45
- 6 - A 20 DFFE 1 3 0 2 |CONTROL1:1|:47
- 8 - A 20 DFFE 1 3 0 3 |CONTROL1:1|:49
- 7 - A 04 DFFE 1 2 0 30 |CONTROL1:1|:53
- 2 - A 12 DFFE 1 4 1 1 |CONTROL1:1|:55
- 1 - B 21 DFFE 1 4 0 18 |CONTROL1:1|state1 (|CONTROL1:1|:57)
- 7 - A 09 DFFE 1 4 0 18 |CONTROL1:1|state0 (|CONTROL1:1|:58)
- 4 - B 12 DFFE 1 3 0 6 |CONTROL1:1|freq13 (|CONTROL1:1|:59)
- 2 - B 13 DFFE 1 4 0 5 |CONTROL1:1|freq12 (|CONTROL1:1|:60)
- 6 - B 14 DFFE 1 4 0 6 |CONTROL1:1|freq11 (|CONTROL1:1|:61)
- 2 - B 14 DFFE 1 4 0 7 |CONTROL1:1|freq10 (|CONTROL1:1|:62)
- 6 - B 15 DFFE 1 4 0 8 |CONTROL1:1|freq9 (|CONTROL1:1|:63)
- 4 - B 15 DFFE 1 4 0 8 |CONTROL1:1|freq8 (|CONTROL1:1|:64)
- 8 - B 19 DFFE 1 4 0 8 |CONTROL1:1|freq7 (|CONTROL1:1|:65)
- 6 - B 02 DFFE 1 3 0 8 |CONTROL1:1|freq6 (|CONTROL1:1|:66)
- 3 - B 01 DFFE 1 3 0 9 |CONTROL1:1|freq5 (|CONTROL1:1|:67)
- 6 - B 11 DFFE 1 4 0 9 |CONTROL1:1|freq4 (|CONTROL1:1|:68)
- 5 - B 08 DFFE 1 3 0 12 |CONTROL1:1|freq3 (|CONTROL1:1|:69)
- 1 - B 03 DFFE 1 3 0 11 |CONTROL1:1|freq2 (|CONTROL1:1|:70)
- 1 - B 01 DFFE 1 4 0 7 |CONTROL1:1|freq1 (|CONTROL1:1|:71)
- 2 - B 01 DFFE 1 3 0 11 |CONTROL1:1|freq0 (|CONTROL1:1|:72)
- 5 - B 05 OR2 ! 0 3 0 7 |CONTROL1:1|:228
- 1 - B 12 OR2 ! 0 2 0 22 |CONTROL1:1|:244
- 7 - B 12 OR2 0 3 0 1 |CONTROL1:1|:577
- 7 - B 08 OR2 0 3 0 1 |CONTROL1:1|:637
- 8 - B 03 OR2 0 3 0 1 |CONTROL1:1|:643
- 3 - B 05 OR2 ! 0 4 0 6 |CONTROL1:1|:806
- 1 - B 05 OR2 ! 0 4 0 5 |CONTROL1:1|:815
- 2 - B 05 OR2 ! 0 4 0 5 |CONTROL1:1|:824
- 3 - B 12 OR2 0 4 0 1 |CONTROL1:1|:1188
- 5 - B 12 OR2 0 4 0 1 |CONTROL1:1|:1200
- 3 - B 08 OR2 0 4 0 1 |CONTROL1:1|:1344
- 4 - B 08 OR2 0 4 0 1 |CONTROL1:1|:1350
- 3 - B 03 OR2 s 0 4 0 1 |CONTROL1:1|~1362~1
- 6 - B 03 OR2 0 4 0 1 |CONTROL1:1|:1365
- 4 - B 03 AND2 0 3 0 3 |CONTROL1:1|:1625
- 8 - B 05 AND2 0 2 0 1 |CONTROL1:1|:1631
- 3 - B 16 AND2 s 0 4 0 1 |CONTROL1:1|~1689~1
- 5 - B 16 AND2 s 0 4 0 1 |CONTROL1:1|~1689~2
- 6 - B 16 AND2 s 0 4 0 1 |CONTROL1:1|~1689~3
- 2 - B 16 OR2 0 4 0 1 |CONTROL1:1|:1929
- 8 - A 09 AND2 0 2 0 16 |CONTROL1:1|:1957
- 7 - A 12 AND2 s 0 2 0 4 |CONTROL1:1|~1965~1
- 1 - B 23 AND2 s 0 2 0 5 |CONTROL1:1|~1965~2
- 8 - B 22 AND2 s 0 2 0 4 |CONTROL1:1|~1965~3
- 2 - B 03 AND2 s 0 2 0 1 |CONTROL1:1|~1965~4
- 8 - A 12 AND2 s 0 2 0 2 |CONTROL1:1|~1965~5
- 3 - A 09 OR2 ! 0 2 0 27 |CONTROL1:1|:1965
- 6 - B 12 OR2 0 4 0 1 |CONTROL1:1|:2127
- 3 - B 13 OR2 s 0 4 0 1 |CONTROL1:1|~2139~1
- 6 - B 13 OR2 s 0 4 0 1 |CONTROL1:1|~2139~2
- 3 - B 14 OR2 s 0 4 0 1 |CONTROL1:1|~2148~1
- 4 - B 14 OR2 s 0 4 0 1 |CONTROL1:1|~2148~2
- 5 - B 14 OR2 s 0 4 0 1 |CONTROL1:1|~2157~1
- 7 - B 14 OR2 s 0 4 0 1 |CONTROL1:1|~2157~2
- 3 - B 15 OR2 s 0 4 0 1 |CONTROL1:1|~2166~1
- 5 - B 15 OR2 s 0 4 0 1 |CONTROL1:1|~2166~2
- 7 - B 15 OR2 s 0 4 0 1 |CONTROL1:1|~2175~1
- 8 - B 15 OR2 s 0 4 0 1 |CONTROL1:1|~2175~2
- 5 - B 13 OR2 s 0 4 0 1 |CONTROL1:1|~2184~1
- 7 - B 19 OR2 s 0 4 0 1 |CONTROL1:1|~2184~2
- 3 - B 02 OR2 s 0 4 0 1 |CONTROL1:1|~2193~1
- 8 - B 02 OR2 s 0 4 0 1 |CONTROL1:1|~2193~2
- 8 - B 01 OR2 s 0 4 0 1 |CONTROL1:1|~2202~1
- 2 - B 02 OR2 s 0 4 0 1 |CONTROL1:1|~2202~2
- 5 - B 03 OR2 s 0 4 0 10 |CONTROL1:1|~2211~1
- 1 - B 11 OR2 s 0 4 0 1 |CONTROL1:1|~2211~2
- 2 - B 11 OR2 s 0 4 0 1 |CONTROL1:1|~2211~3
- 6 - B 08 OR2 0 4 0 1 |CONTROL1:1|:2217
- 7 - B 03 OR2 0 4 0 1 |CONTROL1:1|:2226
- 2 - B 23 OR2 s 0 4 0 10 |CONTROL1:1|~2238~1
- 5 - B 01 OR2 s 0 4 0 1 |CONTROL1:1|~2238~2
- 4 - B 01 OR2 s 0 3 0 2 |CONTROL1:1|~2247~1
- 6 - B 01 OR2 s 0 3 0 1 |CONTROL1:1|~2247~2
- 7 - B 01 OR2 s 0 4 0 1 |CONTROL1:1|~2247~3
- 5 - B 23 OR2 s 0 4 0 1 |CONTROL1:1|~2292~1
- 4 - B 23 OR2 s 0 4 0 1 |CONTROL1:1|~2301~1
- 3 - B 23 OR2 s 0 4 0 1 |CONTROL1:1|~2310~1
- 4 - B 13 AND2 s ! 0 2 0 11 |CONTROL1:1|~2319~1
- 3 - A 12 AND2 s 0 2 0 1 |CONTROL1:1|~2319~2
- 5 - A 12 OR2 s 0 3 0 1 |CONTROL1:1|~2319~3
- 6 - A 12 OR2 0 3 0 1 |CONTROL1:1|:2327
- 8 - A 05 LCELL s 1 0 1 0 cs4~1
- 2 - A 18 AND2 0 3 0 4 |FILTER:6|LPM_ADD_SUB:70|addcore:adder|:125
- 5 - A 18 AND2 0 2 0 1 |FILTER:6|LPM_ADD_SUB:70|addcore:adder|:129
- 1 - A 18 AND2 0 4 0 2 |FILTER:6|LPM_ADD_SUB:70|addcore:adder|:137
- 6 - A 16 DFFE 1 4 1 0 |FILTER:6|:11
- 4 - A 16 DFFE 1 3 1 0 |FILTER:6|:13
- 3 - A 18 DFFE 1 4 1 0 |FILTER:6|:15
- 4 - A 18 DFFE 1 4 1 0 |FILTER:6|:17
- 1 - A 20 DFFE 1 3 1 0 |FILTER:6|:19
- 7 - A 20 DFFE 1 4 1 0 |FILTER:6|:21
- 1 - A 22 DFFE 1 3 1 0 |FILTER:6|:23
- 7 - A 22 DFFE 1 1 1 0 |FILTER:6|:25
- 1 - A 08 AND2 0 3 0 5 |FREQDIV:2|LPM_ADD_SUB:100|addcore:adder|:125
- 5 - A 08 AND2 0 2 0 1 |FREQDIV:2|LPM_ADD_SUB:100|addcore:adder|:129
- 3 - A 02 AND2 0 4 0 2 |FREQDIV:2|LPM_ADD_SUB:100|addcore:adder|:137
- 7 - A 08 DFFE 1 1 0 30 |FREQDIV:2|:2
- 5 - A 02 DFFE 1 3 0 1 |FREQDIV:2|num7 (|FREQDIV:2|:4)
- 4 - A 02 DFFE 1 2 0 2 |FREQDIV:2|num6 (|FREQDIV:2|:5)
- 2 - A 02 DFFE 1 3 0 2 |FREQDIV:2|num5 (|FREQDIV:2|:6)
- 7 - A 02 DFFE 1 3 0 3 |FREQDIV:2|num4 (|FREQDIV:2|:7)
- 6 - A 02 DFFE 1 2 0 4 |FREQDIV:2|num3 (|FREQDIV:2|:8)
- 4 - A 08 DFFE 1 3 0 1 |FREQDIV:2|num2 (|FREQDIV:2|:9)
- 2 - A 08 DFFE 1 2 0 2 |FREQDIV:2|num1 (|FREQDIV:2|:10)
- 3 - A 08 DFFE 1 0 0 3 |FREQDIV:2|num0 (|FREQDIV:2|:11)
- 1 - A 02 OR2 s 0 3 0 1 |FREQDIV:2|~45~1
- 8 - A 02 OR2 ! 0 4 0 8 |FREQDIV:2|:45
- 4 - B 05 DFFE 1 3 0 7 |KEY_DECODER:35|:6
- 2 - B 06 DFFE 1 3 0 8 |KEY_DECODER:35|:8
- 1 - B 10 DFFE 1 3 0 9 |KEY_DECODER:35|:10
- 4 - B 10 DFFE 1 3 0 7 |KEY_DECODER:35|:12
- 2 - B 07 DFFE 1 3 1 6 |KEY_DECODER:35|:14
- 4 - B 07 DFFE 1 3 1 6 |KEY_DECODER:35|:16
- 6 - B 07 DFFE 1 3 1 6 |KEY_DECODER:35|:18
- 6 - B 10 DFFE 1 3 1 7 |KEY_DECODER:35|:20
- 6 - B 05 DFFE 1 3 1 17 |KEY_DECODER:35|:22
- 3 - B 06 OR2 s ! 0 2 0 1 |KEY_DECODER:35|~196~1
- 1 - B 06 OR2 ! 0 4 0 2 |KEY_DECODER:35|:208
- 8 - B 06 OR2 ! 0 4 0 1 |KEY_DECODER:35|:232
- 6 - B 06 OR2 s ! 0 4 0 3 |KEY_DECODER:35|~295~1
- 7 - B 05 AND2 ! 0 2 0 5 |KEY_DECODER:35|:295
- 7 - B 09 AND2 0 4 0 3 |KEY_DECODER:35|:852
- 7 - B 06 OR2 s 0 4 0 3 |KEY_DECODER:35|~856~1
- 4 - B 09 OR2 ! 0 4 0 5 |KEY_DECODER:35|:864
- 2 - B 09 AND2 0 4 0 4 |KEY_DECODER:35|:876
- 3 - B 07 AND2 0 4 0 5 |KEY_DECODER:35|:888
- 4 - B 06 OR2 s 0 4 0 1 |KEY_DECODER:35|~906~1
- 3 - B 10 AND2 s ! 0 4 0 4 |KEY_DECODER:35|~906~2
- 5 - B 06 OR2 s 0 4 0 1 |KEY_DECODER:35|~906~3
- 7 - B 10 OR2 s 0 4 0 1 |KEY_DECODER:35|~921~1
- 8 - B 10 OR2 s 0 4 0 1 |KEY_DECODER:35|~921~2
- 2 - B 10 OR2 s 0 3 0 1 |KEY_DECODER:35|~936~1
- 5 - B 10 OR2 s 0 4 0 1 |KEY_DECODER:35|~936~2
- - 1 C -- MEM_SGMT 0 9 0 4 |LPM_ROM:15|altrom:srom|segment0_0
- - 2 C -- MEM_SGMT 0 9 0 3 |LPM_ROM:15|altrom:srom|segment0_1
- - 4 C -- MEM_SGMT 0 9 0 2 |LPM_ROM:15|altrom:srom|segment0_2
- - 3 C -- MEM_SGMT 0 9 0 4 |LPM_ROM:15|altrom:srom|segment0_3
- - 1 A -- MEM_SGMT 0 9 0 3 |LPM_ROM:15|altrom:srom|segment0_4
- - 2 A -- MEM_SGMT 0 9 0 2 |LPM_ROM:15|altrom:srom|segment0_5
- - 4 A -- MEM_SGMT 0 9 0 2 |LPM_ROM:15|altrom:srom|segment0_6
- - 3 A -- MEM_SGMT 0 9 0 1 |LPM_ROM:15|altrom:srom|segment0_7
- 3 - A 20 OR2 0 4 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry1
- 3 - A 06 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry2
- 6 - A 06 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry3
- 4 - A 06 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry4
- 2 - A 10 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry5
- 6 - A 03 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry6
- 2 - A 03 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry7
- 5 - A 01 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry8
- 6 - A 04 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry9
- 4 - A 04 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry10
- 4 - A 09 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry11
- 7 - A 16 OR2 0 3 0 2 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry12
- 8 - A 16 OR2 0 3 0 1 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|pcarry13
- 5 - A 20 AND2 0 2 0 1 |PHASE_ADDER:17|LPM_ADD_SUB:228|addcore:adder|:92
- 3 - A 16 DFFE 0 4 0 1 |PHASE_ADDER:17|:32
- 1 - A 16 DFFE 0 5 0 1 |PHASE_ADDER:17|:34
- 2 - A 16 DFFE 0 5 0 1 |PHASE_ADDER:17|:36
- 6 - A 09 DFFE 0 5 0 1 |PHASE_ADDER:17|:38
- 1 - A 04 DFFE 0 5 0 1 |PHASE_ADDER:17|:40
- 5 - A 04 DFFE 0 5 0 1 |PHASE_ADDER:17|:42
- 8 - A 01 DFFE 0 5 0 1 |PHASE_ADDER:17|:44
- 3 - A 03 DFFE 0 5 0 1 |PHASE_ADDER:17|:46
- 4 - A 03 DFFE 0 5 0 1 |PHASE_ADDER:17|:48
- 1 - A 10 DFFE 0 5 0 1 |PHASE_ADDER:17|:50
- 5 - A 06 DFFE 0 5 0 1 |PHASE_ADDER:17|:52
- 2 - A 06 DFFE 0 5 0 1 |PHASE_ADDER:17|:54
- 8 - A 06 DFFE 0 5 0 1 |PHASE_ADDER:17|:56
- 4 - A 20 DFFE 0 5 0 1 |PHASE_ADDER:17|:58
- 2 - A 20 DFFE 0 4 0 1 |PHASE_ADDER:17|:60
- 1 - A 11 DFFE 0 3 0 8 |PHASE_REG:18|buff14 (|PHASE_REG:18|:33)
- 1 - A 07 DFFE 0 3 0 10 |PHASE_REG:18|buff13 (|PHASE_REG:18|:34)
- 7 - A 07 DFFE 0 3 0 10 |PHASE_REG:18|buff12 (|PHASE_REG:18|:35)
- 6 - A 11 DFFE 0 3 0 10 |PHASE_REG:18|buff11 (|PHASE_REG:18|:36)
- 4 - A 11 DFFE 0 3 0 10 |PHASE_REG:18|buff10 (|PHASE_REG:18|:37)
- 5 - A 07 DFFE 0 3 0 10 |PHASE_REG:18|buff9 (|PHASE_REG:18|:38)
- 3 - A 11 DFFE 0 3 0 10 |PHASE_REG:18|buff8 (|PHASE_REG:18|:39)
- 8 - A 07 DFFE 0 3 0 10 |PHASE_REG:18|buff7 (|PHASE_REG:18|:40)
- 4 - A 07 DFFE 0 3 0 10 |PHASE_REG:18|buff6 (|PHASE_REG:18|:41)
- 5 - A 10 DFFE 0 3 0 10 |PHASE_REG:18|buff5 (|PHASE_REG:18|:42)
- 8 - A 11 DFFE 0 3 0 2 |PHASE_REG:18|buff4 (|PHASE_REG:18|:43)
- 3 - A 07 DFFE 0 3 0 2 |PHASE_REG:18|buff3 (|PHASE_REG:18|:44)
- 2 - A 07 DFFE 0 3 0 2 |PHASE_REG:18|buff2 (|PHASE_REG:18|:45)
- 5 - A 11 DFFE 0 3 0 2 |PHASE_REG:18|buff1 (|PHASE_REG:18|:46)
- 6 - A 07 DFFE 0 3 0 3 |PHASE_REG:18|buff0 (|PHASE_REG:18|:47)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds.rpt
dds
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 49/ 96( 51%) 30/ 48( 62%) 3/ 48( 6%) 1/16( 6%) 6/16( 37%) 0/16( 0%)
B: 34/ 96( 35%) 32/ 48( 66%) 18/ 48( 37%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 10/ 48( 20%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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