📄 dds.rpt
字号:
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds.rpt
dds
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 9/22( 40%)
A2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
A3 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 2/2 0/2 10/22( 45%)
A4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 10/22( 45%)
A5 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
A6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 12/22( 54%)
A7 8/ 8(100%) 5/ 8( 62%) 8/ 8(100%) 1/2 0/2 10/22( 45%)
A8 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
A9 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 2/2 0/2 10/22( 45%)
A10 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 4/22( 18%)
A11 6/ 8( 75%) 3/ 8( 37%) 6/ 8( 75%) 1/2 0/2 8/22( 36%)
A12 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
A16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 13/22( 59%)
A18 5/ 8( 62%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
A20 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 15/22( 68%)
A22 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
B1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
B2 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 14/22( 63%)
B3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
B4 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B5 8/ 8(100%) 2/ 8( 25%) 7/ 8( 87%) 1/2 0/2 7/22( 31%)
B6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
B7 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 2/2 0/2 3/22( 13%)
B8 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 15/22( 68%)
B9 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
B10 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
B11 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 14/22( 63%)
B12 7/ 8( 87%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
B13 6/ 8( 75%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
B14 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
B15 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
B16 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
B19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
B21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 5/22( 22%)
B22 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
B23 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
B24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 0/8 ( 0%) 4/8 ( 50%) 0/2 2/2 9/22( 40%)
C25 8/8 (100%) 4/8 ( 50%) 0/8 ( 0%) 0/2 2/2 9/22( 40%)
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 39/53 ( 73%)
Total logic cells used: 246/576 ( 42%)
Total embedded cells used: 16/24 ( 66%)
Total EABs used: 2/3 ( 66%)
Average fan-in: 3.24/4 ( 81%)
Total fan-in: 798/2304 ( 34%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 34
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 246
Total flipflops required: 104
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 57/ 576 ( 9%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 7 8 6 8 2 8 8 6 8 3 6 8 8 0 0 0 8 0 5 0 8 0 2 0 0 101/8
B: 8 8 8 8 8 8 8 8 3 8 8 7 0 6 8 8 6 0 0 8 0 1 2 8 8 145/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
Total: 15 16 14 16 10 16 16 14 11 11 14 15 16 6 8 8 14 0 5 8 8 1 4 8 8 246/16
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds.rpt
dds
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- INPUT 0 0 0 75 clk
67 - - B -- INPUT 0 0 0 1 key0
66 - - B -- INPUT 0 0 0 1 key1
65 - - B -- INPUT 0 0 0 1 key2
64 - - B -- INPUT 0 0 0 1 key3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds.rpt
dds
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
73 - - A -- OUTPUT 0 1 0 0 co0
78 - - - 24 OUTPUT 0 1 0 0 co1
79 - - - 24 OUTPUT 0 1 0 0 co2
80 - - - 23 OUTPUT 0 1 0 0 co3
81 - - - 22 OUTPUT 0 1 0 0 co4
83 - - - 13 OUTPUT 0 1 0 0 co5
3 - - - 12 OUTPUT 0 1 0 0 co6
5 - - - 05 OUTPUT 0 1 0 0 co7
18 - - A -- OUTPUT 0 0 0 0 cs1
70 - - A -- OUTPUT 0 0 0 0 cs2
25 - - B -- OUTPUT 0 0 0 0 cs3
69 - - A -- OUTPUT 0 1 0 0 cs4
58 - - C -- OUTPUT 0 1 0 0 data0
54 - - - 21 OUTPUT 0 1 0 0 data1
53 - - - 20 OUTPUT 0 1 0 0 data2
52 - - - 19 OUTPUT 0 1 0 0 data3
51 - - - 18 OUTPUT 0 1 0 0 data4
50 - - - 17 OUTPUT 0 1 0 0 data5
49 - - - 16 OUTPUT 0 1 0 0 data6
48 - - - 15 OUTPUT 0 1 0 0 data7
17 - - A -- OUTPUT 0 1 0 0 int
16 - - A -- OUTPUT 0 1 0 0 kin0
7 - - - 03 OUTPUT 0 1 0 0 kin1
8 - - - 03 OUTPUT 0 1 0 0 kin2
36 - - - 07 OUTPUT 0 1 0 0 kin3
37 - - - 09 OUTPUT 0 1 0 0 ko0
24 - - B -- OUTPUT 0 1 0 0 ko1
23 - - B -- OUTPUT 0 1 0 0 ko2
22 - - B -- OUTPUT 0 1 0 0 ko3
35 - - - 06 OUTPUT 0 1 0 0 kv
9 - - - 02 OUTPUT 0 1 0 0 so0
21 - - B -- OUTPUT 0 1 0 0 so1
6 - - - 04 OUTPUT 0 1 0 0 so2
27 - - C -- OUTPUT 0 1 0 0 so3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds.rpt
dds
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 07 DFFE 2 0 0 3 |ANTISHAKE:36|s13 (|ANTISHAKE:36|:10)
- 6 - B 04 DFFE 2 0 0 3 |ANTISHAKE:36|s12 (|ANTISHAKE:36|:11)
- 3 - B 04 DFFE 2 0 0 3 |ANTISHAKE:36|s11 (|ANTISHAKE:36|:12)
- 3 - A 01 DFFE 2 0 0 3 |ANTISHAKE:36|s10 (|ANTISHAKE:36|:13)
- 5 - B 07 DFFE 1 1 0 2 |ANTISHAKE:36|s23 (|ANTISHAKE:36|:14)
- 8 - B 04 DFFE 1 1 0 2 |ANTISHAKE:36|s22 (|ANTISHAKE:36|:15)
- 4 - B 04 DFFE 1 1 0 2 |ANTISHAKE:36|s21 (|ANTISHAKE:36|:16)
- 4 - A 01 DFFE 1 1 0 2 |ANTISHAKE:36|s20 (|ANTISHAKE:36|:17)
- 8 - B 07 AND2 s 0 2 1 0 |ANTISHAKE:36|~120~1
- 1 - B 07 AND2 0 2 1 5 |ANTISHAKE:36|:120
- 2 - B 04 OR2 s ! 0 2 1 0 |ANTISHAKE:36|~121~1
- 5 - B 04 OR2 ! 0 2 1 5 |ANTISHAKE:36|:121
- 7 - B 04 OR2 s ! 0 2 1 0 |ANTISHAKE:36|~122~1
- 1 - B 04 OR2 ! 0 2 1 5 |ANTISHAKE:36|:122
- 1 - A 01 OR2 s ! 0 2 1 0 |ANTISHAKE:36|~123~1
- 6 - A 01 OR2 ! 0 2 1 5 |ANTISHAKE:36|:123
- 7 - B 11 OR2 0 4 0 1 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry4
- 8 - B 11 OR2 0 3 0 3 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry5
- 2 - B 19 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry6
- 4 - B 19 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry7
- 1 - B 19 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry8
- 2 - B 24 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry9
- 5 - B 24 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry10
- 6 - B 24 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry11
- 7 - B 24 OR2 0 3 0 1 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|pcarry12
- 4 - B 16 AND2 ! 0 2 0 1 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|:122
- 3 - B 11 OR2 0 4 0 3 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|:172
- 5 - B 11 OR2 s 0 4 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|~173~1
- 5 - B 19 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|:175
- 6 - B 19 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|:176
- 1 - B 16 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|:177
- 4 - B 24 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|:178
- 1 - B 24 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|:179
- 8 - B 24 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:466|addcore:adder|:180
- 1 - B 08 OR2 0 4 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|pcarry2
- 8 - B 08 OR2 0 4 0 3 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|pcarry3
- 4 - B 02 OR2 0 4 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:111
- 5 - B 02 OR2 0 4 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:115
- 3 - B 19 AND2 0 2 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:119
- 2 - B 15 AND2 0 2 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:123
- 1 - B 15 AND2 0 2 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:127
- 1 - B 14 AND2 0 2 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:131
- 8 - B 14 AND2 0 2 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:135
- 1 - B 02 OR2 0 4 0 1 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:151
- 7 - B 02 OR2 0 4 0 1 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:152
- 3 - B 24 OR2 s 0 3 0 1 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|~159~1
- 2 - B 12 OR2 0 3 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:159
- 4 - B 11 OR2 0 4 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:161
- 2 - B 08 OR2 0 4 0 2 |CONTROL1:1|LPM_ADD_SUB:485|addcore:adder|:162
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