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📄 phase_adder.rpt

📁 这是用VHDL语言编写的一个DDS频率合成器的源程序
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_LC1_A5  = LCELL( _EQ006);
  _EQ006 =  _LC1_A3 &  M6
         #  _LC1_A3 &  Prev_Phase6
         #  M6 &  Prev_Phase6;

-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry7' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_C17', type is buried 
_LC4_C17 = LCELL( _EQ007);
  _EQ007 =  _LC1_A5 &  M7
         #  _LC1_A5 &  Prev_Phase7
         #  M7 &  Prev_Phase7;

-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry8' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C17', type is buried 
_LC6_C17 = LCELL( _EQ008);
  _EQ008 =  _LC4_C17 &  M8
         #  _LC4_C17 &  Prev_Phase8
         #  M8 &  Prev_Phase8;

-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry9' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = LCELL( _EQ009);
  _EQ009 =  _LC6_C17 &  M9
         #  _LC6_C17 &  Prev_Phase9
         #  M9 &  Prev_Phase9;

-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry10' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ010);
  _EQ010 =  _LC2_C17 &  M10
         #  _LC2_C17 &  Prev_Phase10
         #  M10 &  Prev_Phase10;

-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry11' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ011);
  _EQ011 =  _LC4_B18 &  M11
         #  _LC4_B18 &  Prev_Phase11
         #  M11 &  Prev_Phase11;

-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry12' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = LCELL( _EQ012);
  _EQ012 =  _LC7_B18 &  M12
         #  _LC7_B18 &  Prev_Phase12
         #  M12 &  Prev_Phase12;

-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry13' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B18', type is buried 
_LC1_B18 = LCELL( _EQ013);
  _EQ013 =  _LC8_B18 &  M13
         #  _LC8_B18 &  Prev_Phase13
         #  M13 &  Prev_Phase13;

-- Node name is '|LPM_ADD_SUB:228|addcore:adder|:92' from file "addcore.tdf" line 308, column 28
-- Equation name is '_LC5_A5', type is buried 
_LC5_A5  = LCELL( _EQ014);
  _EQ014 =  M0 &  Prev_Phase0;

-- Node name is ':32' 
-- Equation name is '_LC1_C17', type is buried 
_LC1_C17 = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 =  _LC1_B18 & !Prev_Phase14 & !reset
         # !_LC1_B18 &  Prev_Phase14 & !reset;

-- Node name is ':34' 
-- Equation name is '_LC3_B18', type is buried 
_LC3_B18 = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 =  _LC8_B18 &  M13 &  Prev_Phase13 & !reset
         #  _LC8_B18 & !M13 & !Prev_Phase13 & !reset
         # !_LC8_B18 &  M13 & !Prev_Phase13 & !reset
         # !_LC8_B18 & !M13 &  Prev_Phase13 & !reset;

-- Node name is ':36' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 =  _LC7_B18 &  M12 &  Prev_Phase12 & !reset
         #  _LC7_B18 & !M12 & !Prev_Phase12 & !reset
         # !_LC7_B18 &  M12 & !Prev_Phase12 & !reset
         # !_LC7_B18 & !M12 &  Prev_Phase12 & !reset;

-- Node name is ':38' 
-- Equation name is '_LC6_B18', type is buried 
_LC6_B18 = DFFE( _EQ018, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ018 =  _LC4_B18 &  M11 &  Prev_Phase11 & !reset
         #  _LC4_B18 & !M11 & !Prev_Phase11 & !reset
         # !_LC4_B18 &  M11 & !Prev_Phase11 & !reset
         # !_LC4_B18 & !M11 &  Prev_Phase11 & !reset;

-- Node name is ':40' 
-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = DFFE( _EQ019, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ019 =  _LC2_C17 &  M10 &  Prev_Phase10 & !reset
         #  _LC2_C17 & !M10 & !Prev_Phase10 & !reset
         # !_LC2_C17 &  M10 & !Prev_Phase10 & !reset
         # !_LC2_C17 & !M10 &  Prev_Phase10 & !reset;

-- Node name is ':42' 
-- Equation name is '_LC3_C17', type is buried 
_LC3_C17 = DFFE( _EQ020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ020 =  _LC6_C17 &  M9 &  Prev_Phase9 & !reset
         #  _LC6_C17 & !M9 & !Prev_Phase9 & !reset
         # !_LC6_C17 &  M9 & !Prev_Phase9 & !reset
         # !_LC6_C17 & !M9 &  Prev_Phase9 & !reset;

-- Node name is ':44' 
-- Equation name is '_LC5_C17', type is buried 
_LC5_C17 = DFFE( _EQ021, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ021 =  _LC4_C17 &  M8 &  Prev_Phase8 & !reset
         #  _LC4_C17 & !M8 & !Prev_Phase8 & !reset
         # !_LC4_C17 &  M8 & !Prev_Phase8 & !reset
         # !_LC4_C17 & !M8 &  Prev_Phase8 & !reset;

-- Node name is ':46' 
-- Equation name is '_LC7_C17', type is buried 
_LC7_C17 = DFFE( _EQ022, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ022 =  _LC1_A5 &  M7 &  Prev_Phase7 & !reset
         #  _LC1_A5 & !M7 & !Prev_Phase7 & !reset
         # !_LC1_A5 &  M7 & !Prev_Phase7 & !reset
         # !_LC1_A5 & !M7 &  Prev_Phase7 & !reset;

-- Node name is ':48' 
-- Equation name is '_LC3_A5', type is buried 
_LC3_A5  = DFFE( _EQ023, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ023 =  _LC1_A3 &  M6 &  Prev_Phase6 & !reset
         #  _LC1_A3 & !M6 & !Prev_Phase6 & !reset
         # !_LC1_A3 &  M6 & !Prev_Phase6 & !reset
         # !_LC1_A3 & !M6 &  Prev_Phase6 & !reset;

-- Node name is ':50' 
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = DFFE( _EQ024, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ024 =  _LC7_A3 &  M5 &  Prev_Phase5 & !reset
         #  _LC7_A3 & !M5 & !Prev_Phase5 & !reset
         # !_LC7_A3 &  M5 & !Prev_Phase5 & !reset
         # !_LC7_A3 & !M5 &  Prev_Phase5 & !reset;

-- Node name is ':52' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = DFFE( _EQ025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ025 =  _LC6_A3 &  M4 &  Prev_Phase4 & !reset
         #  _LC6_A3 & !M4 & !Prev_Phase4 & !reset
         # !_LC6_A3 &  M4 & !Prev_Phase4 & !reset
         # !_LC6_A3 & !M4 &  Prev_Phase4 & !reset;

-- Node name is ':54' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = DFFE( _EQ026, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ026 =  _LC4_A3 &  M3 &  Prev_Phase3 & !reset
         #  _LC4_A3 & !M3 & !Prev_Phase3 & !reset
         # !_LC4_A3 &  M3 & !Prev_Phase3 & !reset
         # !_LC4_A3 & !M3 &  Prev_Phase3 & !reset;

-- Node name is ':56' 
-- Equation name is '_LC8_A3', type is buried 
_LC8_A3  = DFFE( _EQ027, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ027 =  _LC2_A5 &  M2 &  Prev_Phase2 & !reset
         #  _LC2_A5 & !M2 & !Prev_Phase2 & !reset
         # !_LC2_A5 & !M2 &  Prev_Phase2 & !reset
         # !_LC2_A5 &  M2 & !Prev_Phase2 & !reset;

-- Node name is ':58' 
-- Equation name is '_LC6_A5', type is buried 
_LC6_A5  = DFFE( _EQ028, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ028 =  _LC5_A5 &  M1 &  Prev_Phase1 & !reset
         # !_LC5_A5 & !M1 &  Prev_Phase1 & !reset
         # !_LC5_A5 &  M1 & !Prev_Phase1 & !reset
         #  _LC5_A5 & !M1 & !Prev_Phase1 & !reset;

-- Node name is ':60' 
-- Equation name is '_LC4_A5', type is buried 
_LC4_A5  = DFFE( _EQ029, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ029 =  M0 & !Prev_Phase0 & !reset
         # !M0 &  Prev_Phase0 & !reset;



Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\phase_adder.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,496K

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