📄 phase_adder.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
5 - - - 05 OUTPUT 0 1 0 0 Current_Phase0
35 - - - 06 OUTPUT 0 1 0 0 Current_Phase1
6 - - - 04 OUTPUT 0 1 0 0 Current_Phase2
7 - - - 03 OUTPUT 0 1 0 0 Current_Phase3
18 - - A -- OUTPUT 0 1 0 0 Current_Phase4
17 - - A -- OUTPUT 0 1 0 0 Current_Phase5
72 - - A -- OUTPUT 0 1 0 0 Current_Phase6
58 - - C -- OUTPUT 0 1 0 0 Current_Phase7
59 - - C -- OUTPUT 0 1 0 0 Current_Phase8
61 - - C -- OUTPUT 0 1 0 0 Current_Phase9
66 - - B -- OUTPUT 0 1 0 0 Current_Phase10
64 - - B -- OUTPUT 0 1 0 0 Current_Phase11
65 - - B -- OUTPUT 0 1 0 0 Current_Phase12
51 - - - 18 OUTPUT 0 1 0 0 Current_Phase13
62 - - C -- OUTPUT 0 1 0 0 Current_Phase14
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\phase_adder.rpt
phase_adder
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 05 OR2 4 0 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry1
- 4 - A 03 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry2
- 6 - A 03 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry3
- 7 - A 03 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry4
- 1 - A 03 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry5
- 1 - A 05 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry6
- 4 - C 17 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry7
- 6 - C 17 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry8
- 2 - C 17 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry9
- 4 - B 18 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry10
- 7 - B 18 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry11
- 8 - B 18 OR2 2 1 0 2 |LPM_ADD_SUB:228|addcore:adder|pcarry12
- 1 - B 18 OR2 2 1 0 1 |LPM_ADD_SUB:228|addcore:adder|pcarry13
- 5 - A 05 AND2 2 0 0 1 |LPM_ADD_SUB:228|addcore:adder|:92
- 1 - C 17 DFFE + 2 1 1 0 :32
- 3 - B 18 DFFE + 3 1 1 0 :34
- 5 - B 18 DFFE + 3 1 1 0 :36
- 6 - B 18 DFFE + 3 1 1 0 :38
- 2 - B 18 DFFE + 3 1 1 0 :40
- 3 - C 17 DFFE + 3 1 1 0 :42
- 5 - C 17 DFFE + 3 1 1 0 :44
- 7 - C 17 DFFE + 3 1 1 0 :46
- 3 - A 05 DFFE + 3 1 1 0 :48
- 3 - A 03 DFFE + 3 1 1 0 :50
- 5 - A 03 DFFE + 3 1 1 0 :52
- 2 - A 03 DFFE + 3 1 1 0 :54
- 8 - A 03 DFFE + 3 1 1 0 :56
- 6 - A 05 DFFE + 3 1 1 0 :58
- 4 - A 05 DFFE + 3 0 1 0 :60
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\phase_adder.rpt
phase_adder
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 8/ 48( 16%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 7/ 96( 7%) 0/ 48( 0%) 5/ 48( 10%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 8/ 96( 8%) 0/ 48( 0%) 5/ 48( 10%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\phase_adder.rpt
phase_adder
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 15 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\phase_adder.rpt
phase_adder
** EQUATIONS **
clk : INPUT;
M0 : INPUT;
M1 : INPUT;
M2 : INPUT;
M3 : INPUT;
M4 : INPUT;
M5 : INPUT;
M6 : INPUT;
M7 : INPUT;
M8 : INPUT;
M9 : INPUT;
M10 : INPUT;
M11 : INPUT;
M12 : INPUT;
M13 : INPUT;
Prev_Phase0 : INPUT;
Prev_Phase1 : INPUT;
Prev_Phase2 : INPUT;
Prev_Phase3 : INPUT;
Prev_Phase4 : INPUT;
Prev_Phase5 : INPUT;
Prev_Phase6 : INPUT;
Prev_Phase7 : INPUT;
Prev_Phase8 : INPUT;
Prev_Phase9 : INPUT;
Prev_Phase10 : INPUT;
Prev_Phase11 : INPUT;
Prev_Phase12 : INPUT;
Prev_Phase13 : INPUT;
Prev_Phase14 : INPUT;
reset : INPUT;
-- Node name is 'Current_Phase0'
-- Equation name is 'Current_Phase0', type is output
Current_Phase0 = _LC4_A5;
-- Node name is 'Current_Phase1'
-- Equation name is 'Current_Phase1', type is output
Current_Phase1 = _LC6_A5;
-- Node name is 'Current_Phase2'
-- Equation name is 'Current_Phase2', type is output
Current_Phase2 = _LC8_A3;
-- Node name is 'Current_Phase3'
-- Equation name is 'Current_Phase3', type is output
Current_Phase3 = _LC2_A3;
-- Node name is 'Current_Phase4'
-- Equation name is 'Current_Phase4', type is output
Current_Phase4 = _LC5_A3;
-- Node name is 'Current_Phase5'
-- Equation name is 'Current_Phase5', type is output
Current_Phase5 = _LC3_A3;
-- Node name is 'Current_Phase6'
-- Equation name is 'Current_Phase6', type is output
Current_Phase6 = _LC3_A5;
-- Node name is 'Current_Phase7'
-- Equation name is 'Current_Phase7', type is output
Current_Phase7 = _LC7_C17;
-- Node name is 'Current_Phase8'
-- Equation name is 'Current_Phase8', type is output
Current_Phase8 = _LC5_C17;
-- Node name is 'Current_Phase9'
-- Equation name is 'Current_Phase9', type is output
Current_Phase9 = _LC3_C17;
-- Node name is 'Current_Phase10'
-- Equation name is 'Current_Phase10', type is output
Current_Phase10 = _LC2_B18;
-- Node name is 'Current_Phase11'
-- Equation name is 'Current_Phase11', type is output
Current_Phase11 = _LC6_B18;
-- Node name is 'Current_Phase12'
-- Equation name is 'Current_Phase12', type is output
Current_Phase12 = _LC5_B18;
-- Node name is 'Current_Phase13'
-- Equation name is 'Current_Phase13', type is output
Current_Phase13 = _LC3_B18;
-- Node name is 'Current_Phase14'
-- Equation name is 'Current_Phase14', type is output
Current_Phase14 = _LC1_C17;
-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ001);
_EQ001 = M1 & Prev_Phase1
# M0 & Prev_Phase0 & Prev_Phase1
# M0 & M1 & Prev_Phase0;
-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = LCELL( _EQ002);
_EQ002 = _LC2_A5 & Prev_Phase2
# _LC2_A5 & M2
# M2 & Prev_Phase2;
-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A3', type is buried
_LC6_A3 = LCELL( _EQ003);
_EQ003 = _LC4_A3 & M3
# _LC4_A3 & Prev_Phase3
# M3 & Prev_Phase3;
-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = LCELL( _EQ004);
_EQ004 = _LC6_A3 & M4
# _LC6_A3 & Prev_Phase4
# M4 & Prev_Phase4;
-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ005);
_EQ005 = _LC7_A3 & M5
# _LC7_A3 & Prev_Phase5
# M5 & Prev_Phase5;
-- Node name is '|LPM_ADD_SUB:228|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A5', type is buried
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