control1.vhd

这是用VHDL语言编写的一个DDS频率合成器的源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity control1 is
port
(
	clk	:in std_logic;
	keydata	:in std_logic_vector (3 downto 0);-- "1010" enter "1011" clear 1100 reset
	keyvalid:in std_logic;
	--WR:	in std_logic;
	--RD:	in std_logic;
	C51OUT	:out std_logic_vector (7 downto 0);
	M	:out std_logic_vector (15 downto 0);
	MEN	:out std_logic;
	PRreset:out std_logic;
	Interrupt :out std_logic
);
end control1;

architecture behave of control1 is
type state_type is (SetM,Working,Setting);
signal state:state_type; 
signal freq:std_logic_vector(15 downto 0);
begin
	process(clk)
	begin
		if(clk'event and clk='1') then
			case state is
				when Working=>
					PRreset<='0';
					if (keyvalid='1' and keydata>="0000" and keydata<="1001") then
						state<=Setting;
						freq<= (freq(14 downto 0)& "0")+ (freq(12 downto 0)& "000") + ("000000000000"& keydata);
						C51OUT<="0000" & keydata;
						Interrupt<='1';
					elsif (keyvalid='1' and keydata="1100") then
						C51OUT<="0000" & keydata;
						freq<="0000000000000100";
						state<=SetM;
						MEN<='1';
						Interrupt<='1';
					else 
						MEN<='0';
						Interrupt<='0';
					end if;
				when Setting=>
					PRreset<='0';
					if (keyvalid='1') then
						C51OUT<= "0000" & keydata;
						Interrupt<='1';
						if (keydata="1011") then state<=Working;
						elsif (keydata="1100") then
							freq<="0000000000000100";
							state<=SetM;
							MEN<='1';
						elsif (keydata="1010") then 
												state<=SetM;
												MEN<='1';
						elsif (keydata>="0000" and keydata<="1001") then
							if (freq(15)='1') then
									freq<="0000000000000100";
								state<=SetM;
								MEN<='1';
								C51OUT<="00001100";
								Interrupt<='1';
							else
									freq<= (freq(14 downto 0)& "0")+ (freq(12 downto 0)& "000") + ("000000000000"& keydata);
							end if;
						end if;
					else Interrupt<='0';
					end if;
				when SetM=>
					if (freq="0000000000000000") then M<="0000000000000100";
					else M<=freq;
					end if;
					PRreset<='1';
					state<=Working;
					Interrupt<='0';
					freq<="0000000000000000";
				when others=>
					freq<="000000000000100";
					MEN<='1';
					state<=SetM;
					PRreset<='0';
			end case;
		end if;
	end process;
end behave;