filter.vhd

这是用VHDL语言编写的一个DDS频率合成器的源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity filter is
port
(
	din		:in std_logic_vector (7 downto 0);
	ah,clk	:in std_logic;
	dout	:out std_logic_vector (7 downto 0)
);
end filter;

architecture behave of filter is
begin
	process(clk)
	begin
		if (clk'event and clk='1') then
			if (ah='1') then dout<=128-din;
			else dout<=din+128;
			end if;
		end if;
	end process;
end behave;