control.vhd

这是用VHDL语言编写的一个DDS频率合成器的源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity control is
port
(
	clk	:in std_logic;
	reset:in std_logic;
	keydata	:in std_logic_vector (3 downto 0);-- "1010" enter "1011" clear 1100 reset
	keyvalid:in std_logic;
	WR:	in std_logic;
	RD:	in std_logic;
	C51IN	:in std_logic_vector (15 downto 0);
	C51OUT	:out std_logic_vector (15 downto 0);
	M	:out std_logic_vector (12 downto 0);
	DataOut	:out std_logic_vector (7 downto 0);
	WrRAM	:out std_logic;
	Interrupt :out std_logic
);
end control;

architecture behave of control is
type state_type is (InitData,Setting,Working);
signal state:state_type; 
signal addr:std_logic_vector(15 downto 0);
signal freq:std_logic_vector(23 downto 0);
signal freqback:std_logic_vector(23 downto 0);
signal restore:std_logic;
begin
	process(clk)
	begin
		if(clk'event and clk='1') then
			if (reset='1') then state<=InitData;
			else
			case state is
				when InitData=>
					if (WR='0') then state<=Working;
					--elsif (keyvalid='1' and keydata="reset") --change address;
					--elsif DataOut<=C51IN
					end if;
				when Working=>
					if (keyvalid='1') then state<=Setting;
					elsif (keyvalid='1' and keydata="1100") then state<=InitData;
					end if;
					-- send to MC51
				when Setting=>
					if (keyvalid='1' and (keydata="1011" or keydata="1010") ) then
						state<=Working;
						if (keydata="1011") then restore<='1';
						elsif (keydata="1010") then restore<='0';
						end if;
					elsif (keyvalid='1' and keydata="1100") then state<=InitData;
					-- send signal to MC51
					end if;
				when others=>
					state<=Working;
			end case;
			end if;
		end if;
	end process;
	process(clk)
	begin
		if (clk'event and clk='1') then
			if (reset='1') then
				freqback<="000000000000000000000101";
				freq<="000000000000000000000101";
				addr<="0000000000000000";
			else
			case state is
				when InitData=>
					if (WR='1' and RD='1') then
						C51OUT<= addr;--address of data needed and send interrupt;
						Interrupt<='1';
					else Interrupt<='0';
					end if;
					if (WR='1' and RD='0') then 
						DataOut<= C51IN(7 downto 0); -- read data from C51
						WrRAM<='1'; --Write data to 
						addr<=addr+1;
					end if;
					if (WR='1' and RD='0' and addr="000111111111111") then
						addr<="1111111111111111";
					elsif (WR='1' and keyvalid='1' and keydata="1100") then
						addr="0000000000000000";
					end if;
				when Working=>
					--output M,adder and reg enable;
					WrRAM<='0';--set cs signal;
				when Setting=>
					if (keyvalid='1')then
						C51OUT<= keydata;
						freq<= freq(23 downto 0) & keydata;
						Interrupt<='1';
					else Interrupt<='0';
					--send interrupt;
			end case;
			end if;
		end if;
	end process;
end behave;