filter.rpt

这是用VHDL语言编写的一个DDS频率合成器的源程序

   -      4     -    B    24       DFFE   +            3    0    1    0  :23
   -      8     -    A    02       DFFE   +            1    0    1    0  :25


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\filter.rpt
filter

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       1/ 96(  1%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
B:       5/ 96(  5%)     3/ 48(  6%)     3/ 48(  6%)    3/16( 18%)      6/16( 37%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\filter.rpt
filter

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        8         clk


Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\filter.rpt
filter

** EQUATIONS **

ah       : INPUT;
clk      : INPUT;
din0     : INPUT;
din1     : INPUT;
din2     : INPUT;
din3     : INPUT;
din4     : INPUT;
din5     : INPUT;
din6     : INPUT;
din7     : INPUT;

-- Node name is 'dout0' 
-- Equation name is 'dout0', type is output 
dout0    =  _LC8_A2;

-- Node name is 'dout1' 
-- Equation name is 'dout1', type is output 
dout1    =  _LC4_B24;

-- Node name is 'dout2' 
-- Equation name is 'dout2', type is output 
dout2    =  _LC2_B24;

-- Node name is 'dout3' 
-- Equation name is 'dout3', type is output 
dout3    =  _LC8_B24;

-- Node name is 'dout4' 
-- Equation name is 'dout4', type is output 
dout4    =  _LC1_B24;

-- Node name is 'dout5' 
-- Equation name is 'dout5', type is output 
dout5    =  _LC7_B24;

-- Node name is 'dout6' 
-- Equation name is 'dout6', type is output 
dout6    =  _LC1_B9;

-- Node name is 'dout7' 
-- Equation name is 'dout7', type is output 
dout7    =  _LC8_B9;

-- Node name is '|LPM_ADD_SUB:70|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B24', type is buried 
_LC5_B24 = LCELL( _EQ001);
  _EQ001 = !din0 & !din1 & !din2;

-- Node name is '|LPM_ADD_SUB:70|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B24', type is buried 
_LC6_B24 = LCELL( _EQ002);
  _EQ002 = !din3 &  _LC5_B24;

-- Node name is '|LPM_ADD_SUB:70|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B24', type is buried 
_LC3_B24 = LCELL( _EQ003);
  _EQ003 = !din3 & !din4 & !din5 &  _LC5_B24;

-- Node name is ':11' 
-- Equation name is '_LC8_B9', type is buried 
_LC8_B9  = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  ah &  din7 & !_LC3_B24
         #  ah &  din6 &  din7
         # !din6 & !din7 &  _LC3_B24
         # !ah & !din7;

-- Node name is ':13' 
-- Equation name is '_LC1_B9', type is buried 
_LC1_B9  = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  din6 &  _LC3_B24
         #  ah & !din6 & !_LC3_B24
         # !ah &  din6;

-- Node name is ':15' 
-- Equation name is '_LC7_B24', type is buried 
_LC7_B24 = DFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 = !din4 &  din5 &  _LC6_B24
         #  ah & !din5 & !_LC6_B24
         #  ah &  din4 & !din5
         # !ah &  din5;

-- Node name is ':17' 
-- Equation name is '_LC1_B24', type is buried 
_LC1_B24 = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 = !din3 &  din4 &  _LC5_B24
         #  ah & !din4 & !_LC5_B24
         #  ah &  din3 & !din4
         # !ah &  din4;

-- Node name is ':19' 
-- Equation name is '_LC8_B24', type is buried 
_LC8_B24 = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  din3 &  _LC5_B24
         #  ah & !din3 & !_LC5_B24
         # !ah &  din3;

-- Node name is ':21' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 = !din0 & !din1 &  din2
         #  ah &  din1 & !din2
         #  ah &  din0 & !din2
         # !ah &  din2;

-- Node name is ':23' 
-- Equation name is '_LC4_B24', type is buried 
_LC4_B24 = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  ah &  din0 & !din1
         # !din0 &  din1
         # !ah &  din1;

-- Node name is ':25' 
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = DFFE( din0, GLOBAL( clk),  VCC,  VCC,  VCC);



Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\filter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:02
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,339K