📄 key_decoder.rpt
字号:
Type Fan-out Name
INPUT 9 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\key_decoder.rpt
key_decoder
** EQUATIONS **
clk : INPUT;
keyin0 : INPUT;
keyin1 : INPUT;
keyin2 : INPUT;
keyin3 : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC1_A15;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC2_A14;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC3_A13;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC5_A18;
-- Node name is 'keyout0'
-- Equation name is 'keyout0', type is output
keyout0 = _LC8_A15;
-- Node name is 'keyout1'
-- Equation name is 'keyout1', type is output
keyout1 = _LC4_A14;
-- Node name is 'keyout2'
-- Equation name is 'keyout2', type is output
keyout2 = _LC6_A14;
-- Node name is 'keyout3'
-- Equation name is 'keyout3', type is output
keyout3 = _LC5_A15;
-- Node name is 'valid'
-- Equation name is 'valid', type is output
valid = _LC1_A18;
-- Node name is ':6'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = DFFE( _EQ001, GLOBAL(!clk), VCC, VCC, VCC);
_EQ001 = !_LC3_A15 & _LC5_A18
# _LC2_A13 & _LC5_A18
# !_LC1_A13 & _LC2_A13 & _LC3_A15;
-- Node name is ':8'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = DFFE( _EQ002, GLOBAL(!clk), VCC, VCC, VCC);
_EQ002 = _LC7_A13 & !_LC8_A13
# _LC3_A13 & !_LC3_A15;
-- Node name is ':10'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = DFFE( _EQ003, GLOBAL(!clk), VCC, VCC, VCC);
_EQ003 = _LC2_A14 & _LC6_A18
# _LC2_A14 & _LC7_A14
# _LC2_A18 & _LC7_A14;
-- Node name is ':12'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( _EQ004, GLOBAL(!clk), VCC, VCC, VCC);
_EQ004 = _LC1_A15 & _LC6_A18
# _LC7_A15 & !_LC8_A14;
-- Node name is ':14'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = DFFE( _EQ005, GLOBAL(!clk), VCC, VCC, VCC);
_EQ005 = _LC8_A14
# _LC2_A15
# _LC4_A15
# _LC3_A14;
-- Node name is ':16'
-- Equation name is '_LC6_A14', type is buried
_LC6_A14 = DFFE( _EQ006, GLOBAL(!clk), VCC, VCC, VCC);
_EQ006 = !_LC3_A14 & !_LC5_A14
# !_LC3_A14 & !_LC3_A18
# !_LC7_A14;
-- Node name is ':18'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = DFFE( _EQ007, GLOBAL(!clk), VCC, VCC, VCC);
_EQ007 = _LC7_A14
# _LC3_A18 & _LC8_A14;
-- Node name is ':20'
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = DFFE( _EQ008, GLOBAL(!clk), VCC, VCC, VCC);
_EQ008 = _LC6_A18
# _LC3_A14 & !_LC8_A14
# !_LC2_A15 & !_LC8_A14;
-- Node name is ':22'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = DFFE( _EQ009, GLOBAL(!clk), VCC, VCC, VCC);
_EQ009 = _LC3_A18 & _LC8_A14
# _LC3_A14 & _LC3_A18
# !_LC3_A14 & _LC4_A18 & !_LC8_A14;
-- Node name is '~204~1'
-- Equation name is '~204~1', location is LC5_A13, type is buried.
-- synthesized logic cell
_LC5_A13 = LCELL( _EQ010);
_EQ010 = keyin0 & keyin1;
-- Node name is ':216'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ011);
_EQ011 = keyin0 & keyin1 & !keyin2 & keyin3;
-- Node name is ':240'
-- Equation name is '_LC8_A13', type is buried
!_LC8_A13 = _LC8_A13~NOT;
_LC8_A13~NOT = LCELL( _EQ012);
_EQ012 = !keyin2
# !keyin3
# keyin0
# !keyin1;
-- Node name is '~719~1'
-- Equation name is '~719~1', location is LC1_A13, type is buried.
-- synthesized logic cell
!_LC1_A13 = _LC1_A13~NOT;
_LC1_A13~NOT = LCELL( _EQ013);
_EQ013 = _LC4_A13
# keyin2 & !keyin3 & _LC5_A13;
-- Node name is ':719'
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = LCELL( _EQ014);
_EQ014 = !_LC2_A13
# !_LC1_A13;
-- Node name is ':1108'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ015);
_EQ015 = _LC4_A14 & !_LC5_A15 & _LC6_A14 & _LC8_A15;
-- Node name is ':1120'
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = LCELL( _EQ016);
_EQ016 = _LC4_A14 & _LC5_A15 & !_LC6_A14 & _LC8_A15;
-- Node name is ':1124'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = LCELL( _EQ017);
_EQ017 = _LC3_A18 & _LC5_A14;
-- Node name is ':1125'
-- Equation name is '_LC2_A15', type is buried
!_LC2_A15 = _LC2_A15~NOT;
_LC2_A15~NOT = LCELL( _EQ018);
_EQ018 = _LC5_A14
# _LC1_A14 & _LC3_A18;
-- Node name is ':1132'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = LCELL( _EQ019);
_EQ019 = !_LC4_A14 & _LC5_A15 & _LC6_A14 & _LC8_A15;
-- Node name is ':1144'
-- Equation name is '_LC8_A14', type is buried
!_LC8_A14 = _LC8_A14~NOT;
_LC8_A14~NOT = LCELL( _EQ020);
_EQ020 = !_LC5_A15
# !_LC6_A14
# !_LC4_A14
# _LC8_A15;
-- Node name is ':1179'
-- Equation name is '_LC7_A14', type is buried
_LC7_A14 = LCELL( _EQ021);
_EQ021 = !_LC3_A14 & !_LC8_A14
# !_LC3_A18 & !_LC8_A14;
-- Node name is ':1193'
-- Equation name is '_LC6_A18', type is buried
_LC6_A18 = LCELL( _EQ022);
_EQ022 = !_LC3_A18 & _LC8_A14;
-- Node name is '~1208~1'
-- Equation name is '~1208~1', location is LC2_A13, type is buried.
-- synthesized logic cell
!_LC2_A13 = _LC2_A13~NOT;
_LC2_A13~NOT = LCELL( _EQ023);
_EQ023 = keyin0 & !keyin1 & keyin2 & keyin3
# !keyin0 & keyin1 & keyin2 & keyin3;
-- Node name is '~1222~1'
-- Equation name is '~1222~1', location is LC6_A13, type is buried.
-- synthesized logic cell
_LC6_A13 = LCELL( _EQ024);
_EQ024 = keyin0 & !keyin1 & keyin2 & keyin3
# keyin0 & keyin1 & keyin2 & !keyin3;
-- Node name is '~1222~2'
-- Equation name is '~1222~2', location is LC3_A15, type is buried.
-- synthesized logic cell
!_LC3_A15 = _LC3_A15~NOT;
_LC3_A15~NOT = LCELL( _EQ025);
_EQ025 = !_LC1_A14 & !_LC3_A14 & !_LC5_A14 & !_LC8_A14;
-- Node name is '~1222~3'
-- Equation name is '~1222~3', location is LC7_A13, type is buried.
-- synthesized logic cell
_LC7_A13 = LCELL( _EQ026);
_EQ026 = _LC3_A15 & _LC6_A13
# _LC3_A13 & !_LC4_A13;
-- Node name is '~1237~1'
-- Equation name is '~1237~1', location is LC2_A18, type is buried.
-- synthesized logic cell
_LC2_A18 = LCELL( _EQ027);
_EQ027 = _LC3_A18 & _LC5_A14
# _LC1_A14 & _LC3_A18;
-- Node name is '~1252~1'
-- Equation name is '~1252~1', location is LC6_A15, type is buried.
-- synthesized logic cell
_LC6_A15 = LCELL( _EQ028);
_EQ028 = _LC1_A14 & !_LC5_A14
# _LC3_A14;
-- Node name is '~1252~2'
-- Equation name is '~1252~2', location is LC7_A15, type is buried.
-- synthesized logic cell
_LC7_A15 = LCELL( _EQ029);
_EQ029 = _LC1_A15 & !_LC5_A14
# _LC1_A15 & !_LC3_A18
# _LC3_A18 & _LC6_A15;
-- Node name is ':1261'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = LCELL( _EQ030);
_EQ030 = _LC3_A18 & _LC5_A14
# _LC1_A14 & _LC3_A18;
Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\key_decoder.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,466K
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