📄 dds1.rpt
字号:
- 1 - B 01 DFFE 1 1 0 9 |FREQDIV:71|:2
- 7 - B 07 DFFE 1 3 0 1 |FREQDIV:71|num7 (|FREQDIV:71|:4)
- 6 - B 07 DFFE 1 2 0 2 |FREQDIV:71|num6 (|FREQDIV:71|:5)
- 3 - B 07 DFFE 1 3 0 2 |FREQDIV:71|num5 (|FREQDIV:71|:6)
- 8 - B 07 DFFE 1 3 0 3 |FREQDIV:71|num4 (|FREQDIV:71|:7)
- 5 - B 07 DFFE 1 2 0 4 |FREQDIV:71|num3 (|FREQDIV:71|:8)
- 4 - B 08 DFFE 1 3 0 1 |FREQDIV:71|num2 (|FREQDIV:71|:9)
- 1 - B 08 DFFE 1 2 0 2 |FREQDIV:71|num1 (|FREQDIV:71|:10)
- 3 - B 08 DFFE 1 0 0 3 |FREQDIV:71|num0 (|FREQDIV:71|:11)
- 1 - B 07 OR2 s 0 3 0 1 |FREQDIV:71|~45~1
- 2 - B 07 OR2 ! 0 4 0 8 |FREQDIV:71|:45
- 2 - B 01 AND2 0 3 0 5 |FREQDIV:72|LPM_ADD_SUB:100|addcore:adder|:125
- 8 - B 02 AND2 0 2 0 1 |FREQDIV:72|LPM_ADD_SUB:100|addcore:adder|:129
- 5 - B 03 AND2 0 4 0 2 |FREQDIV:72|LPM_ADD_SUB:100|addcore:adder|:137
- 2 - B 05 DFFE 0 2 0 9 |FREQDIV:72|:2
- 7 - B 03 DFFE 0 4 0 1 |FREQDIV:72|num7 (|FREQDIV:72|:4)
- 6 - B 03 DFFE 0 3 0 2 |FREQDIV:72|num6 (|FREQDIV:72|:5)
- 3 - B 03 DFFE 0 4 0 2 |FREQDIV:72|num5 (|FREQDIV:72|:6)
- 8 - B 03 DFFE 0 4 0 3 |FREQDIV:72|num4 (|FREQDIV:72|:7)
- 4 - B 03 DFFE 0 3 0 4 |FREQDIV:72|num3 (|FREQDIV:72|:8)
- 5 - B 01 DFFE 0 4 0 1 |FREQDIV:72|num2 (|FREQDIV:72|:9)
- 3 - B 01 DFFE 0 3 0 2 |FREQDIV:72|num1 (|FREQDIV:72|:10)
- 4 - B 01 DFFE 0 1 0 3 |FREQDIV:72|num0 (|FREQDIV:72|:11)
- 2 - B 03 OR2 s 0 3 0 1 |FREQDIV:72|~45~1
- 1 - B 03 OR2 ! 0 4 0 8 |FREQDIV:72|:45
- 5 - B 05 AND2 0 3 0 5 |FREQDIV:73|LPM_ADD_SUB:100|addcore:adder|:125
- 3 - B 04 AND2 0 2 0 1 |FREQDIV:73|LPM_ADD_SUB:100|addcore:adder|:129
- 5 - B 04 AND2 0 4 0 2 |FREQDIV:73|LPM_ADD_SUB:100|addcore:adder|:137
- 6 - B 05 DFFE 0 2 0 9 |FREQDIV:73|:2
- 6 - B 04 DFFE 0 4 0 1 |FREQDIV:73|num7 (|FREQDIV:73|:4)
- 1 - B 05 DFFE 0 3 0 2 |FREQDIV:73|num6 (|FREQDIV:73|:5)
- 4 - B 04 DFFE 0 4 0 2 |FREQDIV:73|num5 (|FREQDIV:73|:6)
- 8 - B 04 DFFE 0 4 0 3 |FREQDIV:73|num4 (|FREQDIV:73|:7)
- 7 - B 04 DFFE 0 3 0 4 |FREQDIV:73|num3 (|FREQDIV:73|:8)
- 7 - B 05 DFFE 0 4 0 1 |FREQDIV:73|num2 (|FREQDIV:73|:9)
- 3 - B 05 DFFE 0 3 0 2 |FREQDIV:73|num1 (|FREQDIV:73|:10)
- 4 - B 05 DFFE 0 1 0 3 |FREQDIV:73|num0 (|FREQDIV:73|:11)
- 2 - B 04 OR2 s 0 3 0 1 |FREQDIV:73|~45~1
- 1 - B 04 OR2 ! 0 4 0 8 |FREQDIV:73|:45
- 5 - B 23 DFFE 0 4 0 11 |KEY_DECODER:35|:6
- 2 - B 22 DFFE 0 4 0 10 |KEY_DECODER:35|:8
- 8 - B 13 DFFE 0 4 0 11 |KEY_DECODER:35|:10
- 6 - B 22 DFFE 0 4 0 8 |KEY_DECODER:35|:12
- 6 - B 14 DFFE 0 5 1 4 |KEY_DECODER:35|:14
- 5 - B 13 DFFE 0 5 1 4 |KEY_DECODER:35|:16
- 3 - B 13 DFFE 0 4 1 4 |KEY_DECODER:35|:18
- 1 - B 14 DFFE 0 5 1 4 |KEY_DECODER:35|:20
- 4 - B 14 DFFE 0 5 0 1 |KEY_DECODER:35|:22
- 5 - B 21 OR2 s ! 2 0 0 1 |KEY_DECODER:35|~204~1
- 6 - B 21 OR2 ! 4 0 0 2 |KEY_DECODER:35|:216
- 7 - B 21 OR2 s 2 0 0 1 |KEY_DECODER:35|~228~1
- 4 - B 21 OR2 ! 4 0 0 2 |KEY_DECODER:35|:240
- 3 - B 21 OR2 s ! 2 2 0 2 |KEY_DECODER:35|~363~1
- 1 - B 23 AND2 ! 0 2 0 12 |KEY_DECODER:35|:363
- 1 - B 24 AND2 0 4 0 5 |KEY_DECODER:35|:1108
- 2 - B 24 OR2 ! 0 4 0 5 |KEY_DECODER:35|:1120
- 8 - B 14 OR2 ! 0 3 0 2 |KEY_DECODER:35|:1125
- 5 - B 24 AND2 0 4 0 8 |KEY_DECODER:35|:1132
- 3 - B 24 OR2 ! 0 4 0 9 |KEY_DECODER:35|:1144
- 6 - B 13 OR2 0 3 0 1 |KEY_DECODER:35|:1179
- 4 - B 13 AND2 0 2 0 1 |KEY_DECODER:35|:1193
- 2 - B 21 OR2 s 2 2 0 2 |KEY_DECODER:35|~1199~1
- 8 - B 21 OR2 s 4 0 0 1 |KEY_DECODER:35|~1222~1
- 1 - B 13 AND2 s ! 0 4 0 3 |KEY_DECODER:35|~1222~2
- 1 - B 21 OR2 s 0 4 0 1 |KEY_DECODER:35|~1222~3
- 7 - B 13 OR2 s 0 3 0 1 |KEY_DECODER:35|~1237~1
- 4 - B 22 OR2 s 0 3 0 1 |KEY_DECODER:35|~1252~1
- 2 - B 13 OR2 s 0 2 0 4 |KEY_DECODER:35|~1252~2
- 7 - B 22 OR2 s 0 4 0 1 |KEY_DECODER:35|~1252~3
- 3 - B 14 OR2 0 3 0 1 |KEY_DECODER:35|:1261
- - 1 C -- MEM_SGMT 0 9 0 4 |LPM_ROM:15|altrom:srom|segment0_0
- - 3 C -- MEM_SGMT 0 9 0 3 |LPM_ROM:15|altrom:srom|segment0_1
- - 2 C -- MEM_SGMT 0 9 0 2 |LPM_ROM:15|altrom:srom|segment0_2
- - 4 C -- MEM_SGMT 0 9 0 4 |LPM_ROM:15|altrom:srom|segment0_3
- - 2 B -- MEM_SGMT 0 9 0 3 |LPM_ROM:15|altrom:srom|segment0_4
- - 1 B -- MEM_SGMT 0 9 0 2 |LPM_ROM:15|altrom:srom|segment0_5
- - 4 B -- MEM_SGMT 0 9 0 2 |LPM_ROM:15|altrom:srom|segment0_6
- - 3 B -- MEM_SGMT 0 9 0 1 |LPM_ROM:15|altrom:srom|segment0_7
- 1 - A 12 OR2 0 4 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry1
- 1 - A 11 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry2
- 6 - A 11 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry3
- 4 - A 11 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry4
- 5 - A 08 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry5
- 8 - A 08 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry6
- 1 - A 08 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry7
- 4 - A 10 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry8
- 5 - A 10 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry9
- 2 - A 10 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry10
- 8 - A 02 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry11
- 3 - A 03 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry12
- 1 - A 03 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry13
- 2 - A 06 OR2 0 3 0 2 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry14
- 3 - A 06 OR2 0 3 0 1 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|pcarry15
- 2 - A 12 AND2 0 2 0 1 |PHASE_ADDER:62|LPM_ADD_SUB:258|addcore:adder|:100
- 4 - A 06 DFFE 0 4 0 1 |PHASE_ADDER:62|:36
- 6 - A 06 DFFE 0 5 0 1 |PHASE_ADDER:62|:38
- 7 - A 06 DFFE 0 5 0 1 |PHASE_ADDER:62|:40
- 5 - A 03 DFFE 0 5 0 1 |PHASE_ADDER:62|:42
- 6 - A 03 DFFE 0 5 0 1 |PHASE_ADDER:62|:44
- 2 - A 02 DFFE 0 5 0 1 |PHASE_ADDER:62|:46
- 8 - A 10 DFFE 0 5 0 1 |PHASE_ADDER:62|:48
- 6 - A 10 DFFE 0 5 0 1 |PHASE_ADDER:62|:50
- 7 - A 10 DFFE 0 5 0 1 |PHASE_ADDER:62|:52
- 2 - A 08 DFFE 0 5 0 1 |PHASE_ADDER:62|:54
- 6 - A 08 DFFE 0 5 0 1 |PHASE_ADDER:62|:56
- 3 - A 08 DFFE 0 5 0 1 |PHASE_ADDER:62|:58
- 7 - A 11 DFFE 0 5 0 1 |PHASE_ADDER:62|:60
- 3 - A 11 DFFE 0 5 0 1 |PHASE_ADDER:62|:62
- 7 - A 12 DFFE 0 5 0 1 |PHASE_ADDER:62|:64
- 3 - A 12 DFFE 0 5 0 1 |PHASE_ADDER:62|:66
- 5 - A 12 DFFE 0 4 0 1 |PHASE_ADDER:62|:68
- 5 - A 06 DFFE 0 3 0 8 |PHASE_REG:64|buff16 (|PHASE_REG:64|:37)
- 1 - A 06 DFFE 0 3 0 10 |PHASE_REG:64|buff15 (|PHASE_REG:64|:38)
- 8 - A 06 DFFE 0 3 0 10 |PHASE_REG:64|buff14 (|PHASE_REG:64|:39)
- 8 - A 03 DFFE 0 3 0 10 |PHASE_REG:64|buff13 (|PHASE_REG:64|:40)
- 2 - A 03 DFFE 0 3 0 10 |PHASE_REG:64|buff12 (|PHASE_REG:64|:41)
- 1 - A 02 DFFE 0 3 0 10 |PHASE_REG:64|buff11 (|PHASE_REG:64|:42)
- 2 - A 11 DFFE 0 3 0 10 |PHASE_REG:64|buff10 (|PHASE_REG:64|:43)
- 3 - A 10 DFFE 0 3 0 10 |PHASE_REG:64|buff9 (|PHASE_REG:64|:44)
- 1 - A 10 DFFE 0 3 0 10 |PHASE_REG:64|buff8 (|PHASE_REG:64|:45)
- 4 - A 03 DFFE 0 3 0 10 |PHASE_REG:64|buff7 (|PHASE_REG:64|:46)
- 7 - A 08 DFFE 0 3 0 2 |PHASE_REG:64|buff6 (|PHASE_REG:64|:47)
- 4 - A 08 DFFE 0 3 0 2 |PHASE_REG:64|buff5 (|PHASE_REG:64|:48)
- 8 - A 11 DFFE 0 3 0 2 |PHASE_REG:64|buff4 (|PHASE_REG:64|:49)
- 5 - A 11 DFFE 0 3 0 2 |PHASE_REG:64|buff3 (|PHASE_REG:64|:50)
- 8 - A 12 DFFE 0 3 0 2 |PHASE_REG:64|buff2 (|PHASE_REG:64|:51)
- 4 - A 12 DFFE 0 3 0 2 |PHASE_REG:64|buff1 (|PHASE_REG:64|:52)
- 6 - A 12 DFFE 0 3 0 3 |PHASE_REG:64|buff0 (|PHASE_REG:64|:53)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt
dds1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 42/ 96( 43%) 24/ 48( 50%) 26/ 48( 54%) 1/16( 6%) 5/16( 31%) 0/16( 0%)
B: 12/ 96( 12%) 22/ 48( 45%) 22/ 48( 45%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 13/ 96( 13%) 17/ 48( 35%) 12/ 48( 25%) 4/16( 25%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 8/24( 33%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 5/24( 20%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt
dds1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 78 clk
DFF 35 |FREQDIV:2|:2
DFF 10 |FREQDIV:71|:2
DFF 10 |FREQDIV:72|:2
DFF 10 |FREQDIV:73|:2
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt
dds1
** EQUATIONS **
clk : INPUT;
key0 : INPUT;
key1 : INPUT;
key2 : INPUT;
key3 : INPUT;
-- Node name is 'co0'
-- Equation name is 'co0', type is output
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