📄 dds1.rpt
字号:
58 - - C -- OUTPUT 0 1 0 0 data0
54 - - - 21 OUTPUT 0 1 0 0 data1
53 - - - 20 OUTPUT 0 1 0 0 data2
52 - - - 19 OUTPUT 0 1 0 0 data3
51 - - - 18 OUTPUT 0 1 0 0 data4
50 - - - 17 OUTPUT 0 1 0 0 data5
49 - - - 16 OUTPUT 0 1 0 0 data6
48 - - - 15 OUTPUT 0 1 0 0 data7
17 - - A -- OUTPUT 0 1 0 0 int
67 - - B -- OUTPUT 0 1 0 0 ko0
66 - - B -- OUTPUT 0 1 0 0 ko1
65 - - B -- OUTPUT 0 1 0 0 ko2
64 - - B -- OUTPUT 0 1 0 0 ko3
47 - - - 14 OUTPUT 0 1 0 0 kv
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt
dds1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 14 DFFE 1 1 0 2 |ANTISHAKE1:50|s1 (|ANTISHAKE1:50|:4)
- 2 - B 14 DFFE 1 1 0 1 |ANTISHAKE1:50|s2 (|ANTISHAKE1:50|:5)
- 5 - B 14 AND2 0 2 1 12 |ANTISHAKE1:50|:36
- 1 - A 01 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry4
- 2 - A 04 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry5
- 5 - A 04 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry6
- 1 - A 04 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry7
- 4 - A 22 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry8
- 8 - A 22 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry9
- 3 - A 21 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry10
- 4 - A 21 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry11
- 3 - A 13 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry12
- 7 - A 13 OR2 0 3 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry13
- 2 - A 18 OR2 0 3 0 1 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|pcarry14
- 3 - A 09 OR2 0 4 0 3 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|:190
- 7 - A 09 OR2 s 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:604|addcore:adder|~191~1
- 1 - A 14 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|pcarry2
- 4 - A 09 OR2 0 4 0 3 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|pcarry3
- 2 - A 09 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:119
- 6 - A 04 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:123
- 8 - A 04 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:127
- 5 - A 22 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:131
- 1 - A 22 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:135
- 6 - A 21 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:139
- 1 - A 21 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:143
- 5 - A 13 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:147
- 8 - A 13 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:151
- 3 - A 18 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:155
- 6 - A 09 OR2 0 2 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:166
- 8 - A 09 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:167
- 4 - A 04 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:168
- 3 - A 04 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:169
- 7 - A 22 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:170
- 6 - A 22 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:171
- 8 - A 21 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:172
- 7 - A 21 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:173
- 6 - A 13 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:174
- 4 - A 13 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:175
- 7 - A 15 OR2 0 4 0 1 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:176
- 4 - A 18 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:177
- 4 - A 17 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:179
- 4 - A 20 OR2 0 4 0 2 |CONTROL1:63|LPM_ADD_SUB:625|addcore:adder|:180
- 4 - C 05 DFFE 1 1 1 0 |CONTROL1:63|:7
- 1 - C 12 DFFE 1 1 1 0 |CONTROL1:63|:9
- 2 - C 13 DFFE 1 1 1 0 |CONTROL1:63|:11
- 4 - C 21 DFFE 1 1 1 0 |CONTROL1:63|:13
- 8 - A 23 DFFE 1 4 1 3 |CONTROL1:63|:15
- 2 - A 24 DFFE 1 4 1 2 |CONTROL1:63|:17
- 4 - C 24 DFFE 1 4 1 2 |CONTROL1:63|:19
- 1 - A 19 DFFE 1 4 1 2 |CONTROL1:63|:21
- 6 - A 23 DFFE 1 3 0 2 |CONTROL1:63|:23
- 8 - A 07 DFFE 1 3 0 2 |CONTROL1:63|:25
- 8 - A 01 DFFE 1 3 0 2 |CONTROL1:63|:27
- 1 - A 07 DFFE 1 3 0 2 |CONTROL1:63|:29
- 6 - A 05 DFFE 1 3 0 2 |CONTROL1:63|:31
- 4 - A 05 DFFE 1 3 0 2 |CONTROL1:63|:33
- 5 - A 05 DFFE 1 3 0 2 |CONTROL1:63|:35
- 8 - A 05 DFFE 1 3 0 2 |CONTROL1:63|:37
- 1 - A 23 DFFE 1 3 0 2 |CONTROL1:63|:39
- 7 - A 01 DFFE 1 3 0 2 |CONTROL1:63|:41
- 3 - A 05 DFFE 1 3 0 2 |CONTROL1:63|:43
- 4 - A 01 DFFE 1 3 0 2 |CONTROL1:63|:45
- 6 - A 01 DFFE 1 3 0 2 |CONTROL1:63|:47
- 5 - A 15 DFFE 1 3 0 2 |CONTROL1:63|:49
- 2 - A 01 DFFE 1 3 0 2 |CONTROL1:63|:51
- 3 - A 01 DFFE 1 3 0 3 |CONTROL1:63|:53
- 1 - A 05 DFFE 1 2 0 1 |CONTROL1:63|:57
- 2 - C 24 DFFE 1 4 1 0 |CONTROL1:63|:59
- 5 - A 19 DFFE 1 3 0 34 |CONTROL1:63|state1 (|CONTROL1:63|:61)
- 2 - A 05 DFFE 1 3 0 34 |CONTROL1:63|state0 (|CONTROL1:63|:62)
- 1 - A 18 DFFE 1 4 0 12 |CONTROL1:63|freq15 (|CONTROL1:63|:63)
- 2 - A 15 DFFE 1 3 0 3 |CONTROL1:63|freq14 (|CONTROL1:63|:64)
- 8 - A 15 DFFE 1 3 0 5 |CONTROL1:63|freq13 (|CONTROL1:63|:65)
- 2 - A 13 DFFE 1 3 0 6 |CONTROL1:63|freq12 (|CONTROL1:63|:66)
- 1 - A 15 DFFE 1 3 0 8 |CONTROL1:63|freq11 (|CONTROL1:63|:67)
- 2 - A 21 DFFE 1 3 0 8 |CONTROL1:63|freq10 (|CONTROL1:63|:68)
- 1 - A 13 DFFE 1 3 0 8 |CONTROL1:63|freq9 (|CONTROL1:63|:69)
- 2 - A 22 DFFE 1 3 0 8 |CONTROL1:63|freq8 (|CONTROL1:63|:70)
- 5 - A 21 DFFE 1 3 0 8 |CONTROL1:63|freq7 (|CONTROL1:63|:71)
- 7 - A 04 DFFE 1 3 0 8 |CONTROL1:63|freq6 (|CONTROL1:63|:72)
- 1 - A 09 DFFE 1 3 0 8 |CONTROL1:63|freq5 (|CONTROL1:63|:73)
- 5 - A 09 DFFE 1 3 0 8 |CONTROL1:63|freq4 (|CONTROL1:63|:74)
- 2 - A 20 DFFE 1 4 0 12 |CONTROL1:63|freq3 (|CONTROL1:63|:75)
- 1 - A 17 DFFE 1 4 0 11 |CONTROL1:63|freq2 (|CONTROL1:63|:76)
- 2 - A 17 DFFE 1 3 0 7 |CONTROL1:63|freq1 (|CONTROL1:63|:77)
- 3 - A 16 DFFE 1 4 0 12 |CONTROL1:63|freq0 (|CONTROL1:63|:78)
- 5 - B 22 OR2 ! 0 3 0 6 |CONTROL1:63|:325
- 2 - A 23 OR2 ! 0 2 0 11 |CONTROL1:63|:341
- 1 - A 24 OR2 ! 0 2 0 4 |CONTROL1:63|:352
- 8 - A 18 OR2 0 4 0 1 |CONTROL1:63|:816
- 8 - A 20 OR2 0 4 0 1 |CONTROL1:63|:924
- 8 - A 17 OR2 0 4 0 1 |CONTROL1:63|:933
- 3 - A 23 OR2 0 4 0 1 |CONTROL1:63|:996
- 8 - A 24 OR2 0 4 0 1 |CONTROL1:63|:1005
- 6 - A 24 AND2 ! 0 2 0 9 |CONTROL1:63|:1032
- 1 - B 22 OR2 ! 0 4 0 8 |CONTROL1:63|:1131
- 3 - B 22 OR2 ! 0 4 0 6 |CONTROL1:63|:1140
- 2 - A 19 OR2 ! 0 4 0 9 |CONTROL1:63|:1149
- 3 - A 24 OR2 0 4 0 1 |CONTROL1:63|:1924
- 5 - A 18 OR2 0 4 0 1 |CONTROL1:63|:1987
- 6 - A 18 AND2 0 2 0 1 |CONTROL1:63|:1995
- 5 - A 20 OR2 0 4 0 1 |CONTROL1:63|:2164
- 6 - A 20 OR2 0 4 0 1 |CONTROL1:63|:2175
- 5 - A 17 OR2 0 4 0 1 |CONTROL1:63|:2179
- 6 - A 17 OR2 0 4 0 1 |CONTROL1:63|:2185
- 4 - A 16 AND2 s 0 2 0 1 |CONTROL1:63|~2210~1
- 3 - A 20 AND2 s 0 2 0 5 |CONTROL1:63|~2220~1
- 3 - A 19 OR2 0 4 0 2 |CONTROL1:63|:2239
- 4 - A 23 OR2 0 4 0 1 |CONTROL1:63|:2329
- 1 - A 20 OR2 s ! 0 2 0 2 |CONTROL1:63|~2336~1
- 4 - A 24 OR2 0 4 0 1 |CONTROL1:63|:2336
- 7 - A 18 OR2 0 4 0 1 |CONTROL1:63|:2359
- 7 - A 20 OR2 0 4 0 1 |CONTROL1:63|:2431
- 7 - A 17 OR2 0 4 0 1 |CONTROL1:63|:2437
- 4 - A 19 OR2 0 4 0 1 |CONTROL1:63|:2461
- 3 - A 15 AND2 s 0 4 0 1 |CONTROL1:63|~2532~1
- 3 - A 22 AND2 s 0 4 0 1 |CONTROL1:63|~2532~2
- 5 - A 01 AND2 s 0 4 0 1 |CONTROL1:63|~2532~3
- 4 - A 15 AND2 s 0 4 0 1 |CONTROL1:63|~2532~4
- 6 - A 15 OR2 0 4 0 1 |CONTROL1:63|:2734
- 5 - A 16 AND2 s 0 4 0 2 |CONTROL1:63|~2810~1
- 5 - A 24 OR2 ! 0 2 0 1 |CONTROL1:63|:2810
- 7 - A 19 AND2 s 0 4 0 1 |CONTROL1:63|~2818~1
- 7 - A 05 OR2 0 4 0 1 |CONTROL1:63|:2994
- 3 - A 17 OR2 s 0 2 0 1 |CONTROL1:63|~3127~1
- 1 - A 16 OR2 s 0 4 0 12 |CONTROL1:63|~3127~2
- 2 - A 16 OR2 s 0 4 0 12 |CONTROL1:63|~3127~3
- 6 - A 16 OR2 s 0 4 0 2 |CONTROL1:63|~3136~1
- 7 - A 16 OR2 s 0 4 0 1 |CONTROL1:63|~3136~2
- 8 - A 16 OR2 s 0 4 0 1 |CONTROL1:63|~3136~3
- 1 - C 24 OR2 s 0 4 0 4 |CONTROL1:63|~3172~1
- 5 - A 23 OR2 0 4 0 1 |CONTROL1:63|:3183
- 7 - A 24 OR2 0 4 0 1 |CONTROL1:63|:3187
- 5 - C 24 OR2 s 0 3 0 1 |CONTROL1:63|~3199~1
- 6 - C 24 OR2 s 0 3 0 1 |CONTROL1:63|~3199~2
- 7 - C 24 OR2 s 0 4 0 1 |CONTROL1:63|~3199~3
- 8 - C 24 OR2 s 0 4 0 1 |CONTROL1:63|~3199~4
- 6 - A 19 OR2 s 0 4 0 1 |CONTROL1:63|~3208~1
- 3 - C 24 OR2 s 0 3 0 4 |CONTROL1:63|~3208~2
- 8 - A 19 OR2 s 0 4 0 1 |CONTROL1:63|~3208~3
- 8 - C 22 LCELL s 1 0 1 0 cs4~1
- 1 - C 07 AND2 0 2 0 1 |DELAY:52|LPM_ADD_SUB:83|addcore:adder|:55
- 8 - C 04 DFFE 1 3 0 35 |DELAY:52|:3
- 6 - C 04 DFFE 1 3 0 2 |DELAY:52|s13 (|DELAY:52|:5)
- 7 - C 04 DFFE 1 3 0 3 |DELAY:52|s12 (|DELAY:52|:6)
- 5 - C 04 DFFE 1 3 0 4 |DELAY:52|s11 (|DELAY:52|:7)
- 1 - C 04 DFFE 1 2 0 5 |DELAY:52|s10 (|DELAY:52|:8)
- 3 - C 04 OR2 s 0 4 0 4 |DELAY:52|~45~1
- 2 - C 04 OR2 0 4 0 4 |DELAY:52|:68
- 4 - C 04 OR2 s 0 3 0 2 |DELAY:52|~119~1
- 1 - C 20 AND2 0 3 0 4 |FILTER:6|LPM_ADD_SUB:70|addcore:adder|:125
- 3 - B 17 AND2 0 2 0 1 |FILTER:6|LPM_ADD_SUB:70|addcore:adder|:129
- 1 - B 17 AND2 0 4 0 2 |FILTER:6|LPM_ADD_SUB:70|addcore:adder|:137
- 4 - B 16 DFFE 1 4 1 0 |FILTER:6|:11
- 1 - B 16 DFFE 1 3 1 0 |FILTER:6|:13
- 2 - B 17 DFFE 1 4 1 0 |FILTER:6|:15
- 5 - B 17 DFFE 1 4 1 0 |FILTER:6|:17
- 5 - C 20 DFFE 1 3 1 0 |FILTER:6|:19
- 2 - C 20 DFFE 1 4 1 0 |FILTER:6|:21
- 2 - C 22 DFFE 1 3 1 0 |FILTER:6|:23
- 6 - C 20 DFFE 1 1 1 0 |FILTER:6|:25
- 6 - C 10 AND2 0 3 0 5 |FREQDIV:2|LPM_ADD_SUB:100|addcore:adder|:125
- 5 - C 10 AND2 0 2 0 1 |FREQDIV:2|LPM_ADD_SUB:100|addcore:adder|:129
- 3 - C 03 AND2 0 4 0 2 |FREQDIV:2|LPM_ADD_SUB:100|addcore:adder|:137
- 3 - C 10 DFFE 1 1 0 34 |FREQDIV:2|:2
- 7 - C 03 DFFE 1 3 0 1 |FREQDIV:2|num7 (|FREQDIV:2|:4)
- 6 - C 03 DFFE 1 2 0 2 |FREQDIV:2|num6 (|FREQDIV:2|:5)
- 2 - C 03 DFFE 1 3 0 2 |FREQDIV:2|num5 (|FREQDIV:2|:6)
- 8 - C 03 DFFE 1 3 0 3 |FREQDIV:2|num4 (|FREQDIV:2|:7)
- 5 - C 03 DFFE 1 2 0 4 |FREQDIV:2|num3 (|FREQDIV:2|:8)
- 4 - C 10 DFFE 1 3 0 1 |FREQDIV:2|num2 (|FREQDIV:2|:9)
- 1 - C 10 DFFE 1 2 0 2 |FREQDIV:2|num1 (|FREQDIV:2|:10)
- 2 - C 10 DFFE 1 0 0 3 |FREQDIV:2|num0 (|FREQDIV:2|:11)
- 1 - C 03 OR2 s 0 3 0 1 |FREQDIV:2|~45~1
- 4 - C 03 OR2 ! 0 4 0 8 |FREQDIV:2|:45
- 2 - B 08 AND2 0 3 0 5 |FREQDIV:71|LPM_ADD_SUB:100|addcore:adder|:125
- 5 - B 08 AND2 0 2 0 1 |FREQDIV:71|LPM_ADD_SUB:100|addcore:adder|:129
- 4 - B 07 AND2 0 4 0 2 |FREQDIV:71|LPM_ADD_SUB:100|addcore:adder|:137
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