dds1.rpt

这是用VHDL语言编写的一个DDS频率合成器的源程序

Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/12/2004 19:05:12

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

dds1      EPF10K10LC84-4   5      26     0    4096      66 %    298      51 %

User Pins:                 5      26     0  



Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

dds1@19                           clk
dds1@73                           co0
dds1@78                           co1
dds1@79                           co2
dds1@80                           co3
dds1@81                           co4
dds1@83                           co5
dds1@3                            co6
dds1@5                            co7
dds1@18                           cs1
dds1@70                           cs2
dds1@25                           cs3
dds1@69                           cs4
dds1@58                           data0
dds1@54                           data1
dds1@53                           data2
dds1@52                           data3
dds1@51                           data4
dds1@50                           data5
dds1@49                           data6
dds1@48                           data7
dds1@17                           int
dds1@62                           key0
dds1@61                           key1
dds1@60                           key2
dds1@59                           key3
dds1@67                           ko0
dds1@66                           ko1
dds1@65                           ko2
dds1@64                           ko3


Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt

** EMBEDDED ARRAYS **


|LPM_ROM:15|altrom:srom|content: MEMORY (
               width        =    8;
               depth        =  512;
               segmentsize  =  512;
               mode         = MEM_READONLY#MEM_INITIALIZED;
               file         = "e:\documents\maple8282\my documents\study\dds\maple8282\temp.mif";
         )
         OF SEGMENTS (
               |LPM_ROM:15|altrom:srom|segment0_7,
               |LPM_ROM:15|altrom:srom|segment0_6,
               |LPM_ROM:15|altrom:srom|segment0_5,
               |LPM_ROM:15|altrom:srom|segment0_4,
               |LPM_ROM:15|altrom:srom|segment0_3,
               |LPM_ROM:15|altrom:srom|segment0_2,
               |LPM_ROM:15|altrom:srom|segment0_1,
               |LPM_ROM:15|altrom:srom|segment0_0
);




Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt

** FILE HIERARCHY **



|freqdiv:2|
|freqdiv:2|lpm_add_sub:100|
|freqdiv:2|lpm_add_sub:100|addcore:adder|
|freqdiv:2|lpm_add_sub:100|altshift:result_ext_latency_ffs|
|freqdiv:2|lpm_add_sub:100|altshift:carry_ext_latency_ffs|
|freqdiv:2|lpm_add_sub:100|altshift:oflow_ext_latency_ffs|
|freqdiv:73|
|freqdiv:73|lpm_add_sub:100|
|freqdiv:73|lpm_add_sub:100|addcore:adder|
|freqdiv:73|lpm_add_sub:100|altshift:result_ext_latency_ffs|
|freqdiv:73|lpm_add_sub:100|altshift:carry_ext_latency_ffs|
|freqdiv:73|lpm_add_sub:100|altshift:oflow_ext_latency_ffs|
|freqdiv:72|
|freqdiv:72|lpm_add_sub:100|
|freqdiv:72|lpm_add_sub:100|addcore:adder|
|freqdiv:72|lpm_add_sub:100|altshift:result_ext_latency_ffs|
|freqdiv:72|lpm_add_sub:100|altshift:carry_ext_latency_ffs|
|freqdiv:72|lpm_add_sub:100|altshift:oflow_ext_latency_ffs|
|freqdiv:71|
|freqdiv:71|lpm_add_sub:100|
|freqdiv:71|lpm_add_sub:100|addcore:adder|
|freqdiv:71|lpm_add_sub:100|altshift:result_ext_latency_ffs|
|freqdiv:71|lpm_add_sub:100|altshift:carry_ext_latency_ffs|
|freqdiv:71|lpm_add_sub:100|altshift:oflow_ext_latency_ffs|
|filter:6|
|filter:6|lpm_add_sub:70|
|filter:6|lpm_add_sub:70|addcore:adder|
|filter:6|lpm_add_sub:70|altshift:result_ext_latency_ffs|
|filter:6|lpm_add_sub:70|altshift:carry_ext_latency_ffs|
|filter:6|lpm_add_sub:70|altshift:oflow_ext_latency_ffs|
|filter:6|lpm_add_sub:111|
|filter:6|lpm_add_sub:111|addcore:adder|
|filter:6|lpm_add_sub:111|altshift:result_ext_latency_ffs|
|filter:6|lpm_add_sub:111|altshift:carry_ext_latency_ffs|
|filter:6|lpm_add_sub:111|altshift:oflow_ext_latency_ffs|
|lpm_rom:15|
|lpm_rom:15|altrom:srom|
|key_decoder:35|
|antishake1:50|
|delay:52|
|delay:52|lpm_add_sub:83|
|delay:52|lpm_add_sub:83|addcore:adder|
|delay:52|lpm_add_sub:83|altshift:result_ext_latency_ffs|
|delay:52|lpm_add_sub:83|altshift:carry_ext_latency_ffs|
|delay:52|lpm_add_sub:83|altshift:oflow_ext_latency_ffs|
|phase_adder:62|
|phase_adder:62|lpm_add_sub:258|
|phase_adder:62|lpm_add_sub:258|addcore:adder|
|phase_adder:62|lpm_add_sub:258|altshift:result_ext_latency_ffs|
|phase_adder:62|lpm_add_sub:258|altshift:carry_ext_latency_ffs|
|phase_adder:62|lpm_add_sub:258|altshift:oflow_ext_latency_ffs|
|control1:63|
|control1:63|lpm_add_sub:604|
|control1:63|lpm_add_sub:604|addcore:adder|
|control1:63|lpm_add_sub:604|altshift:result_ext_latency_ffs|
|control1:63|lpm_add_sub:604|altshift:carry_ext_latency_ffs|
|control1:63|lpm_add_sub:604|altshift:oflow_ext_latency_ffs|
|control1:63|lpm_add_sub:625|
|control1:63|lpm_add_sub:625|addcore:adder|
|control1:63|lpm_add_sub:625|altshift:result_ext_latency_ffs|
|control1:63|lpm_add_sub:625|altshift:carry_ext_latency_ffs|
|control1:63|lpm_add_sub:625|altshift:oflow_ext_latency_ffs|
|control1:63|lpm_add_sub:1575|
|control1:63|lpm_add_sub:1575|addcore:adder|
|control1:63|lpm_add_sub:1575|altshift:result_ext_latency_ffs|
|control1:63|lpm_add_sub:1575|altshift:carry_ext_latency_ffs|
|control1:63|lpm_add_sub:1575|altshift:oflow_ext_latency_ffs|
|control1:63|lpm_add_sub:1596|
|control1:63|lpm_add_sub:1596|addcore:adder|
|control1:63|lpm_add_sub:1596|altshift:result_ext_latency_ffs|
|control1:63|lpm_add_sub:1596|altshift:carry_ext_latency_ffs|
|control1:63|lpm_add_sub:1596|altshift:oflow_ext_latency_ffs|
|phase_reg:64|


Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\dds1.rpt
dds1

***** Logic for device 'dds1' compiled without errors.




Device: EPF10K10LC84-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f