📄 ar.rpt
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-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry9' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ009);
_EQ009 = _LC4_B7 & _LC6_B7
# _LC4_B7 & m9
# _LC6_B7 & m9;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry10' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ010);
_EQ010 = _LC4_B11 & _LC7_B7
# _LC7_B7 & m10
# _LC4_B11 & m10;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry11' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_B15', type is buried
_LC2_B15 = LCELL( _EQ011);
_EQ011 = _LC1_B15 & _LC5_B7
# _LC5_B7 & m11
# _LC1_B15 & m11;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry12' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = LCELL( _EQ012);
_EQ012 = _LC2_B15 & _LC8_A18
# _LC2_B15 & m12
# _LC8_A18 & m12;
-- Node name is '|PHASE_ADDER:1|:32'
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !_LC2_A18 & _LC6_A18 & !m13
# !_LC2_A18 & !_LC4_A18 & _LC6_A18
# !_LC4_A18 & _LC6_A18 & !m13
# _LC2_A18 & _LC4_A18 & !_LC6_A18
# _LC4_A18 & !_LC6_A18 & m13
# _LC2_A18 & !_LC6_A18 & m13;
-- Node name is '|PHASE_ADDER:1|:34'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC2_A18 & _LC4_A18 & m13
# !_LC2_A18 & _LC4_A18 & !m13
# _LC2_A18 & !_LC4_A18 & !m13
# !_LC2_A18 & !_LC4_A18 & m13;
-- Node name is '|PHASE_ADDER:1|:36'
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = _LC2_B15 & _LC8_A18 & m12
# _LC2_B15 & !_LC8_A18 & !m12
# !_LC2_B15 & _LC8_A18 & !m12
# !_LC2_B15 & !_LC8_A18 & m12;
-- Node name is '|PHASE_ADDER:1|:38'
-- Equation name is '_LC7_B15', type is buried
_LC7_B15 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = _LC1_B15 & _LC5_B7 & m11
# !_LC1_B15 & _LC5_B7 & !m11
# _LC1_B15 & !_LC5_B7 & !m11
# !_LC1_B15 & !_LC5_B7 & m11;
-- Node name is '|PHASE_ADDER:1|:40'
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = _LC4_B11 & _LC7_B7 & m10
# !_LC4_B11 & _LC7_B7 & !m10
# _LC4_B11 & !_LC7_B7 & !m10
# !_LC4_B11 & !_LC7_B7 & m10;
-- Node name is '|PHASE_ADDER:1|:42'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = _LC4_B7 & _LC6_B7 & m9
# _LC4_B7 & !_LC6_B7 & !m9
# !_LC4_B7 & _LC6_B7 & !m9
# !_LC4_B7 & !_LC6_B7 & m9;
-- Node name is '|PHASE_ADDER:1|:44'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = _LC1_B7 & _LC1_C4 & m8
# !_LC1_B7 & _LC1_C4 & !m8
# _LC1_B7 & !_LC1_C4 & !m8
# !_LC1_B7 & !_LC1_C4 & m8;
-- Node name is '|PHASE_ADDER:1|:46'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = DFFE( _EQ020, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = _LC5_C4 & _LC6_C4 & m7
# !_LC5_C4 & _LC6_C4 & !m7
# _LC5_C4 & !_LC6_C4 & !m7
# !_LC5_C4 & !_LC6_C4 & m7;
-- Node name is '|PHASE_ADDER:1|:48'
-- Equation name is '_LC7_C4', type is buried
_LC7_C4 = DFFE( _EQ021, GLOBAL( clk), VCC, VCC, VCC);
_EQ021 = _LC1_A9 & _LC3_C4 & m6
# !_LC1_A9 & _LC3_C4 & !m6
# _LC1_A9 & !_LC3_C4 & !m6
# !_LC1_A9 & !_LC3_C4 & m6;
-- Node name is '|PHASE_ADDER:1|:50'
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = DFFE( _EQ022, GLOBAL( clk), VCC, VCC, VCC);
_EQ022 = _LC7_C16 & _LC8_C4 & m5
# _LC7_C16 & !_LC8_C4 & !m5
# !_LC7_C16 & _LC8_C4 & !m5
# !_LC7_C16 & !_LC8_C4 & m5;
-- Node name is '|PHASE_ADDER:1|:52'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = DFFE( _EQ023, GLOBAL( clk), VCC, VCC, VCC);
_EQ023 = _LC3_C16 & _LC6_C16 & m4
# !_LC3_C16 & _LC6_C16 & !m4
# _LC3_C16 & !_LC6_C16 & !m4
# !_LC3_C16 & !_LC6_C16 & m4;
-- Node name is '|PHASE_ADDER:1|:54'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = DFFE( _EQ024, GLOBAL( clk), VCC, VCC, VCC);
_EQ024 = _LC2_C16 & _LC6_C24 & m3
# _LC2_C16 & !_LC6_C24 & !m3
# !_LC2_C16 & _LC6_C24 & !m3
# !_LC2_C16 & !_LC6_C24 & m3;
-- Node name is '|PHASE_ADDER:1|:56'
-- Equation name is '_LC4_C16', type is buried
_LC4_C16 = DFFE( _EQ025, GLOBAL( clk), VCC, VCC, VCC);
_EQ025 = _LC5_C12 & _LC5_C16 & m2
# _LC5_C12 & !_LC5_C16 & !m2
# !_LC5_C12 & _LC5_C16 & !m2
# !_LC5_C12 & !_LC5_C16 & m2;
-- Node name is '|PHASE_ADDER:1|:58'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = DFFE( _EQ026, GLOBAL( clk), VCC, VCC, VCC);
_EQ026 = _LC6_C12 & _LC8_C12 & m0 & m1
# _LC6_C12 & !_LC8_C12 & !m1
# _LC6_C12 & !m0 & !m1
# !_LC6_C12 & !_LC8_C12 & m1
# !_LC6_C12 & !m0 & m1
# !_LC6_C12 & _LC8_C12 & m0 & !m1;
-- Node name is '|PHASE_ADDER:1|:60'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = DFFE( _EQ027, GLOBAL( clk), VCC, VCC, VCC);
_EQ027 = _LC8_C12 & !m0
# !_LC8_C12 & m0;
-- Node name is '|PHASE_REG:2|:47' = '|PHASE_REG:2|buff0'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = DFFE( _LC1_C12, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:46' = '|PHASE_REG:2|buff1'
-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = DFFE( _LC3_C12, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:45' = '|PHASE_REG:2|buff2'
-- Equation name is '_LC5_C16', type is buried
_LC5_C16 = DFFE( _LC4_C16, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:44' = '|PHASE_REG:2|buff3'
-- Equation name is '_LC6_C24', type is buried
_LC6_C24 = DFFE( _LC1_C16, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:43' = '|PHASE_REG:2|buff4'
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = DFFE( _LC8_C16, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:42' = '|PHASE_REG:2|buff5'
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = DFFE( _LC4_C4, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:41' = '|PHASE_REG:2|buff6'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = DFFE( _LC7_C4, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:40' = '|PHASE_REG:2|buff7'
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = DFFE( _LC2_C4, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:39' = '|PHASE_REG:2|buff8'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = DFFE( _LC8_B7, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:38' = '|PHASE_REG:2|buff9'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE( _LC2_B7, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:37' = '|PHASE_REG:2|buff10'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = DFFE( _LC3_B7, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:36' = '|PHASE_REG:2|buff11'
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = DFFE( _LC7_B15, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:35' = '|PHASE_REG:2|buff12'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = DFFE( _LC7_A18, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:34' = '|PHASE_REG:2|buff13'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = DFFE( _LC1_A18, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is '|PHASE_REG:2|:33' = '|PHASE_REG:2|buff14'
-- Equation name is '_LC6_A18', type is buried
_LC6_A18 = DFFE( _LC3_A18, GLOBAL(!clk), VCC, VCC, VCC);
Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\ar.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,453K
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