📄 ar.rpt
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- 6 - C 16 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry3
- 7 - C 16 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry4
- 3 - C 04 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry5
- 6 - C 04 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry6
- 1 - C 04 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry7
- 4 - B 07 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry8
- 7 - B 07 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry9
- 5 - B 07 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry10
- 2 - B 15 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry11
- 4 - A 18 OR2 1 2 0 2 |PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry12
- 3 - A 18 DFFE + 1 3 1 1 |PHASE_ADDER:1|:32
- 1 - A 18 DFFE + 1 2 1 1 |PHASE_ADDER:1|:34
- 7 - A 18 DFFE + 1 2 1 1 |PHASE_ADDER:1|:36
- 7 - B 15 DFFE + 1 2 1 1 |PHASE_ADDER:1|:38
- 3 - B 07 DFFE + 1 2 1 1 |PHASE_ADDER:1|:40
- 2 - B 07 DFFE + 1 2 1 1 |PHASE_ADDER:1|:42
- 8 - B 07 DFFE + 1 2 1 1 |PHASE_ADDER:1|:44
- 2 - C 04 DFFE + 1 2 1 1 |PHASE_ADDER:1|:46
- 7 - C 04 DFFE + 1 2 1 1 |PHASE_ADDER:1|:48
- 4 - C 04 DFFE + 1 2 1 1 |PHASE_ADDER:1|:50
- 8 - C 16 DFFE + 1 2 1 1 |PHASE_ADDER:1|:52
- 1 - C 16 DFFE + 1 2 1 1 |PHASE_ADDER:1|:54
- 4 - C 16 DFFE + 1 2 1 1 |PHASE_ADDER:1|:56
- 3 - C 12 DFFE + 2 2 1 1 |PHASE_ADDER:1|:58
- 1 - C 12 DFFE + 1 1 1 1 |PHASE_ADDER:1|:60
- 6 - A 18 DFFE + 0 1 1 1 |PHASE_REG:2|buff14 (|PHASE_REG:2|:33)
- 2 - A 18 DFFE + 0 1 1 2 |PHASE_REG:2|buff13 (|PHASE_REG:2|:34)
- 8 - A 18 DFFE + 0 1 1 2 |PHASE_REG:2|buff12 (|PHASE_REG:2|:35)
- 1 - B 15 DFFE + 0 1 1 2 |PHASE_REG:2|buff11 (|PHASE_REG:2|:36)
- 4 - B 11 DFFE + 0 1 1 2 |PHASE_REG:2|buff10 (|PHASE_REG:2|:37)
- 6 - B 07 DFFE + 0 1 1 2 |PHASE_REG:2|buff9 (|PHASE_REG:2|:38)
- 1 - B 07 DFFE + 0 1 1 2 |PHASE_REG:2|buff8 (|PHASE_REG:2|:39)
- 5 - C 04 DFFE + 0 1 1 2 |PHASE_REG:2|buff7 (|PHASE_REG:2|:40)
- 1 - A 09 DFFE + 0 1 1 2 |PHASE_REG:2|buff6 (|PHASE_REG:2|:41)
- 8 - C 04 DFFE + 0 1 1 2 |PHASE_REG:2|buff5 (|PHASE_REG:2|:42)
- 3 - C 16 DFFE + 0 1 1 2 |PHASE_REG:2|buff4 (|PHASE_REG:2|:43)
- 6 - C 24 DFFE + 0 1 1 2 |PHASE_REG:2|buff3 (|PHASE_REG:2|:44)
- 5 - C 16 DFFE + 0 1 1 2 |PHASE_REG:2|buff2 (|PHASE_REG:2|:45)
- 6 - C 12 DFFE + 0 1 1 2 |PHASE_REG:2|buff1 (|PHASE_REG:2|:46)
- 8 - C 12 DFFE + 0 1 1 3 |PHASE_REG:2|buff0 (|PHASE_REG:2|:47)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\ar.rpt
ar
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 1/ 48( 2%) 4/ 48( 8%) 2/16( 12%) 6/16( 37%) 0/16( 0%)
B: 7/ 96( 7%) 4/ 48( 8%) 2/ 48( 4%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
C: 5/ 96( 5%) 4/ 48( 8%) 4/ 48( 8%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\ar.rpt
ar
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 30 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\ar.rpt
ar
** EQUATIONS **
clk : INPUT;
m0 : INPUT;
m1 : INPUT;
m2 : INPUT;
m3 : INPUT;
m4 : INPUT;
m5 : INPUT;
m6 : INPUT;
m7 : INPUT;
m8 : INPUT;
m9 : INPUT;
m10 : INPUT;
m11 : INPUT;
m12 : INPUT;
m13 : INPUT;
-- Node name is 'cp0'
-- Equation name is 'cp0', type is output
cp0 = _LC1_C12;
-- Node name is 'cp1'
-- Equation name is 'cp1', type is output
cp1 = _LC3_C12;
-- Node name is 'cp2'
-- Equation name is 'cp2', type is output
cp2 = _LC4_C16;
-- Node name is 'cp3'
-- Equation name is 'cp3', type is output
cp3 = _LC1_C16;
-- Node name is 'cp4'
-- Equation name is 'cp4', type is output
cp4 = _LC8_C16;
-- Node name is 'cp5'
-- Equation name is 'cp5', type is output
cp5 = _LC4_C4;
-- Node name is 'cp6'
-- Equation name is 'cp6', type is output
cp6 = _LC7_C4;
-- Node name is 'cp7'
-- Equation name is 'cp7', type is output
cp7 = _LC2_C4;
-- Node name is 'cp8'
-- Equation name is 'cp8', type is output
cp8 = _LC8_B7;
-- Node name is 'cp9'
-- Equation name is 'cp9', type is output
cp9 = _LC2_B7;
-- Node name is 'cp10'
-- Equation name is 'cp10', type is output
cp10 = _LC3_B7;
-- Node name is 'cp11'
-- Equation name is 'cp11', type is output
cp11 = _LC7_B15;
-- Node name is 'cp12'
-- Equation name is 'cp12', type is output
cp12 = _LC7_A18;
-- Node name is 'cp13'
-- Equation name is 'cp13', type is output
cp13 = _LC1_A18;
-- Node name is 'cp14'
-- Equation name is 'cp14', type is output
cp14 = _LC3_A18;
-- Node name is 'pp0'
-- Equation name is 'pp0', type is output
pp0 = _LC8_C12;
-- Node name is 'pp1'
-- Equation name is 'pp1', type is output
pp1 = _LC6_C12;
-- Node name is 'pp2'
-- Equation name is 'pp2', type is output
pp2 = _LC5_C16;
-- Node name is 'pp3'
-- Equation name is 'pp3', type is output
pp3 = _LC6_C24;
-- Node name is 'pp4'
-- Equation name is 'pp4', type is output
pp4 = _LC3_C16;
-- Node name is 'pp5'
-- Equation name is 'pp5', type is output
pp5 = _LC8_C4;
-- Node name is 'pp6'
-- Equation name is 'pp6', type is output
pp6 = _LC1_A9;
-- Node name is 'pp7'
-- Equation name is 'pp7', type is output
pp7 = _LC5_C4;
-- Node name is 'pp8'
-- Equation name is 'pp8', type is output
pp8 = _LC1_B7;
-- Node name is 'pp9'
-- Equation name is 'pp9', type is output
pp9 = _LC6_B7;
-- Node name is 'pp10'
-- Equation name is 'pp10', type is output
pp10 = _LC4_B11;
-- Node name is 'pp11'
-- Equation name is 'pp11', type is output
pp11 = _LC1_B15;
-- Node name is 'pp12'
-- Equation name is 'pp12', type is output
pp12 = _LC8_A18;
-- Node name is 'pp13'
-- Equation name is 'pp13', type is output
pp13 = _LC2_A18;
-- Node name is 'pp14'
-- Equation name is 'pp14', type is output
pp14 = _LC6_A18;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ001);
_EQ001 = _LC6_C12 & m1
# _LC6_C12 & _LC8_C12 & m0
# _LC8_C12 & m0 & m1;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = LCELL( _EQ002);
_EQ002 = _LC5_C12 & _LC5_C16
# _LC5_C12 & m2
# _LC5_C16 & m2;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C16', type is buried
_LC6_C16 = LCELL( _EQ003);
_EQ003 = _LC2_C16 & _LC6_C24
# _LC2_C16 & m3
# _LC6_C24 & m3;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = LCELL( _EQ004);
_EQ004 = _LC3_C16 & _LC6_C16
# _LC6_C16 & m4
# _LC3_C16 & m4;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ005);
_EQ005 = _LC7_C16 & _LC8_C4
# _LC7_C16 & m5
# _LC8_C4 & m5;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = LCELL( _EQ006);
_EQ006 = _LC1_A9 & _LC3_C4
# _LC3_C4 & m6
# _LC1_A9 & m6;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry7' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ007);
_EQ007 = _LC5_C4 & _LC6_C4
# _LC6_C4 & m7
# _LC5_C4 & m7;
-- Node name is '|PHASE_ADDER:1|LPM_ADD_SUB:165|addcore:adder|pcarry8' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ008);
_EQ008 = _LC1_B7 & _LC1_C4
# _LC1_C4 & m8
# _LC1_B7 & m8;
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