📄 control1.rpt
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Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\control1.rpt
control1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 19 OR2 0 4 0 2 |LPM_ADD_SUB:406|addcore:adder|pcarry4
- 6 - B 19 OR2 0 3 0 3 |LPM_ADD_SUB:406|addcore:adder|pcarry5
- 1 - B 06 OR2 0 3 0 3 |LPM_ADD_SUB:406|addcore:adder|pcarry6
- 3 - B 06 OR2 0 3 0 3 |LPM_ADD_SUB:406|addcore:adder|pcarry7
- 1 - B 05 OR2 0 3 0 3 |LPM_ADD_SUB:406|addcore:adder|pcarry8
- 8 - B 05 OR2 0 3 0 3 |LPM_ADD_SUB:406|addcore:adder|pcarry9
- 4 - B 08 OR2 0 3 0 2 |LPM_ADD_SUB:406|addcore:adder|pcarry10
- 3 - B 08 OR2 0 3 0 2 |LPM_ADD_SUB:406|addcore:adder|pcarry11
- 6 - B 08 OR2 0 3 0 1 |LPM_ADD_SUB:406|addcore:adder|pcarry12
- 3 - B 19 OR2 0 4 0 3 |LPM_ADD_SUB:406|addcore:adder|:172
- 8 - B 19 OR2 0 3 0 2 |LPM_ADD_SUB:406|addcore:adder|:173
- 4 - B 22 OR2 0 3 0 1 |LPM_ADD_SUB:406|addcore:adder|:174
- 2 - B 06 OR2 0 3 0 1 |LPM_ADD_SUB:406|addcore:adder|:175
- 4 - B 01 OR2 0 3 0 1 |LPM_ADD_SUB:406|addcore:adder|:176
- 2 - B 05 OR2 0 3 0 1 |LPM_ADD_SUB:406|addcore:adder|:177
- 1 - B 08 OR2 0 3 0 1 |LPM_ADD_SUB:406|addcore:adder|:178
- 5 - B 08 OR2 0 3 0 3 |LPM_ADD_SUB:406|addcore:adder|:179
- 3 - B 24 OR2 0 3 0 2 |LPM_ADD_SUB:406|addcore:adder|:180
- 4 - B 16 OR2 2 2 0 2 |LPM_ADD_SUB:425|addcore:adder|pcarry2
- 1 - B 13 OR2 1 3 0 3 |LPM_ADD_SUB:425|addcore:adder|pcarry3
- 2 - B 19 AND2 0 3 0 2 |LPM_ADD_SUB:425|addcore:adder|:111
- 4 - B 06 OR2 0 4 0 2 |LPM_ADD_SUB:425|addcore:adder|:115
- 6 - B 06 OR2 0 4 0 2 |LPM_ADD_SUB:425|addcore:adder|:119
- 3 - B 05 OR2 0 4 0 2 |LPM_ADD_SUB:425|addcore:adder|:123
- 4 - B 05 OR2 0 4 0 2 |LPM_ADD_SUB:425|addcore:adder|:127
- 7 - B 08 OR2 0 4 0 3 |LPM_ADD_SUB:425|addcore:adder|:131
- 8 - B 08 OR2 s 0 3 0 1 |LPM_ADD_SUB:425|addcore:adder|~159~1
- 2 - B 17 OR2 0 4 0 2 |LPM_ADD_SUB:425|addcore:adder|:159
- 4 - B 13 OR2 2 2 0 2 |LPM_ADD_SUB:425|addcore:adder|:161
- 3 - B 13 OR2 1 3 0 2 |LPM_ADD_SUB:425|addcore:adder|:162
- 7 - B 03 DFFE + 0 3 1 0 :7
- 6 - B 03 DFFE + 0 3 1 0 :9
- 5 - B 03 DFFE + 0 3 1 0 :11
- 3 - B 03 DFFE + 0 3 1 0 :13
- 4 - B 20 DFFE + 1 2 1 0 :15
- 3 - B 20 DFFE + 1 2 1 0 :17
- 2 - B 20 DFFE + 1 2 1 0 :19
- 6 - B 20 DFFE + 1 2 1 0 :21
- 5 - B 24 DFFE + 0 2 1 0 :23
- 2 - B 03 DFFE + 0 2 1 0 :25
- 1 - B 17 DFFE + 0 3 1 0 :27
- 4 - B 11 DFFE + 0 3 1 0 :29
- 2 - B 24 DFFE + 0 3 1 0 :31
- 3 - B 01 DFFE + 0 3 1 0 :33
- 8 - B 24 DFFE + 0 3 1 0 :35
- 6 - B 01 DFFE + 0 3 1 0 :37
- 2 - B 22 DFFE + 0 3 1 0 :39
- 1 - B 03 DFFE + 0 3 1 0 :41
- 8 - B 03 DFFE + 0 3 1 0 :43
- 1 - B 15 DFFE + 0 3 1 0 :45
- 6 - B 22 DFFE + 0 3 1 0 :47
- 4 - B 03 DFFE + 0 3 1 0 :49
- 6 - B 23 DFFE + 0 3 1 0 :51
- 8 - B 22 DFFE + 0 3 1 0 :53
- 8 - B 14 DFFE + 0 3 1 0 :55
- 1 - B 18 DFFE + 1 3 0 20 state1 (:57)
- 3 - B 22 DFFE + 0 4 0 20 state0 (:58)
- 8 - B 17 DFFE + 0 3 0 5 freq13 (:59)
- 6 - B 11 DFFE + 0 3 0 3 freq12 (:60)
- 7 - B 24 DFFE + 0 3 0 4 freq11 (:61)
- 2 - B 01 DFFE + 0 3 0 5 freq10 (:62)
- 6 - B 05 DFFE + 0 3 0 7 freq9 (:63)
- 1 - B 01 DFFE + 0 3 0 7 freq8 (:64)
- 5 - B 06 DFFE + 0 3 0 8 freq7 (:65)
- 2 - B 11 DFFE + 0 3 0 8 freq6 (:66)
- 1 - B 11 DFFE + 0 3 0 8 freq5 (:67)
- 5 - B 19 DFFE + 0 3 0 7 freq4 (:68)
- 4 - B 18 DFFE + 0 3 0 10 freq3 (:69)
- 2 - B 13 DFFE + 0 3 0 11 freq2 (:70)
- 1 - B 16 DFFE + 0 3 0 4 freq1 (:71)
- 8 - B 16 DFFE + 1 2 0 7 freq0 (:72)
- 7 - B 20 OR2 3 0 0 6 :180
- 2 - B 18 AND2 s 0 2 0 2 ~196~1
- 4 - B 23 AND2 s 0 2 0 10 ~196~2
- 6 - B 18 OR2 ! 1 1 0 8 :196
- 7 - B 17 OR2 0 3 0 1 :493
- 8 - B 18 OR2 0 3 0 1 :553
- 8 - B 13 OR2 0 3 0 1 :559
- 1 - B 20 AND2 4 0 0 8 :658
- 5 - B 20 OR2 ! 4 0 0 6 :667
- 8 - B 20 AND2 4 0 0 7 :676
- 3 - B 17 OR2 0 4 0 1 :1040
- 4 - B 17 OR2 0 4 0 1 :1052
- 3 - B 18 OR2 0 4 0 1 :1196
- 5 - B 18 OR2 0 4 0 1 :1202
- 5 - B 13 OR2 s 0 4 0 1 ~1214~1
- 6 - B 13 OR2 0 4 0 1 :1217
- 7 - B 21 AND2 s 0 2 0 2 ~1249~1
- 1 - B 21 AND2 0 3 0 1 :1477
- 7 - B 22 AND2 1 1 0 1 :1483
- 1 - B 22 OR2 ! 0 2 0 18 :1630
- 1 - B 24 AND2 0 2 0 24 :1638
- 2 - B 16 OR2 s 1 1 0 12 ~1764~1
- 5 - B 21 AND2 s ! 0 2 0 1 ~1830~1
- 3 - B 21 OR2 s 0 4 0 1 ~1848~1
- 6 - B 17 OR2 1 3 0 1 :1881
- 5 - B 17 OR2 s 0 4 0 1 ~1893~1
- 8 - B 11 OR2 s 0 4 0 1 ~1893~2
- 4 - B 24 OR2 s 0 3 0 1 ~1902~1
- 6 - B 24 OR2 s 0 4 0 1 ~1902~2
- 2 - B 08 OR2 s 0 3 0 1 ~1911~1
- 8 - B 01 OR2 s 0 4 0 1 ~1911~2
- 5 - B 05 OR2 s 0 3 0 1 ~1920~1
- 7 - B 05 OR2 s 0 4 0 1 ~1920~2
- 5 - B 01 OR2 s 0 3 0 1 ~1929~1
- 7 - B 01 OR2 s 0 4 0 1 ~1929~2
- 7 - B 06 OR2 s 0 3 0 1 ~1938~1
- 8 - B 06 OR2 s 0 4 0 1 ~1938~2
- 5 - B 22 OR2 s 0 3 0 1 ~1947~1
- 7 - B 11 OR2 s 0 4 0 1 ~1947~2
- 5 - B 11 OR2 s 0 4 0 1 ~1956~1
- 1 - B 19 OR2 s 0 4 0 1 ~1956~2
- 6 - B 21 OR2 s 0 4 0 2 ~1965~1
- 4 - B 19 OR2 s 0 3 0 1 ~1965~2
- 3 - B 16 OR2 s 1 2 0 9 ~1965~3
- 3 - B 11 OR2 s 0 4 0 1 ~1965~4
- 7 - B 18 OR2 1 3 0 1 :1971
- 7 - B 13 OR2 1 3 0 1 :1980
- 5 - B 16 OR2 s 1 1 0 1 ~1992~1
- 2 - B 21 AND2 s ! 0 2 0 1 ~2001~1
- 4 - B 21 OR2 s 0 4 0 11 ~2001~2
- 6 - B 16 OR2 s 0 4 0 2 ~2001~3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\control1.rpt
control1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 33/ 96( 34%) 14/ 48( 29%) 20/ 48( 41%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\control1.rpt
control1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 41 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\control1.rpt
control1
** EQUATIONS **
clk : INPUT;
keydata0 : INPUT;
keydata1 : INPUT;
keydata2 : INPUT;
keydata3 : INPUT;
keyvalid : INPUT;
-- Node name is 'C51OUT0'
-- Equation name is 'C51OUT0', type is output
C51OUT0 = _LC6_B20;
-- Node name is 'C51OUT1'
-- Equation name is 'C51OUT1', type is output
C51OUT1 = _LC2_B20;
-- Node name is 'C51OUT2'
-- Equation name is 'C51OUT2', type is output
C51OUT2 = _LC3_B20;
-- Node name is 'C51OUT3'
-- Equation name is 'C51OUT3', type is output
C51OUT3 = _LC4_B20;
-- Node name is 'C51OUT4'
-- Equation name is 'C51OUT4', type is output
C51OUT4 = _LC3_B3;
-- Node name is 'C51OUT5'
-- Equation name is 'C51OUT5', type is output
C51OUT5 = _LC5_B3;
-- Node name is 'C51OUT6'
-- Equation name is 'C51OUT6', type is output
C51OUT6 = _LC6_B3;
-- Node name is 'C51OUT7'
-- Equation name is 'C51OUT7', type is output
C51OUT7 = _LC7_B3;
-- Node name is ':72' = 'freq0'
-- Equation name is 'freq0', location is LC8_B16, type is buried.
freq0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = keydata0 & _LC4_B21
# freq0 & _LC6_B16;
-- Node name is ':71' = 'freq1'
-- Equation name is 'freq1', location is LC1_B16, type is buried.
freq1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC4_B21 & _LC5_B16
# freq1 & _LC6_B16;
-- Node name is ':70' = 'freq2'
-- Equation name is 'freq2', location is LC2_B13, type is buried.
freq2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC1_B24 & _LC7_B13
# _LC1_B24 & _LC8_B13;
-- Node name is ':69' = 'freq3'
-- Equation name is 'freq3', location is LC4_B18, type is buried.
freq3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC1_B24 & _LC7_B18
# _LC1_B24 & _LC8_B18;
-- Node name is ':68' = 'freq4'
-- Equation name is 'freq4', location is LC5_B19, type is buried.
freq4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC4_B19
# _LC3_B11
# freq4 & _LC4_B23;
-- Node name is ':67' = 'freq5'
-- Equation name is 'freq5', location is LC1_B11, type is buried.
freq5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC5_B11
# _LC1_B19
# freq5 & _LC4_B23;
-- Node name is ':66' = 'freq6'
-- Equation name is 'freq6', location is LC2_B11, type is buried.
freq6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC5_B22
# _LC7_B11
# freq6 & _LC4_B23;
-- Node name is ':65' = 'freq7'
-- Equation name is 'freq7', location is LC5_B6, type is buried.
freq7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC7_B6
# _LC8_B6
# freq7 & _LC4_B23;
-- Node name is ':64' = 'freq8'
-- Equation name is 'freq8', location is LC1_B1, type is buried.
freq8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC5_B1
# _LC7_B1
# freq8 & _LC4_B23;
-- Node name is ':63' = 'freq9'
-- Equation name is 'freq9', location is LC6_B5, type is buried.
freq9 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
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