key_decoder.vhd

这是用VHDL语言编写的一个DDS频率合成器的源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity key_decoder is
port
(
	clk	:in std_logic;	--scan clock
	keyin	:in std_logic_vector (3 downto 0);	--the 8 lines of keyboard input
	data	:out std_logic_vector (3 downto 0);	--the data that keyboard inputed
	keyout	:buffer std_logic_vector (3 downto 0);
	valid	:out std_logic
);
end key_decoder;
architecture behave of key_decoder is
begin
	process(clk)
	begin
		if (clk'event and clk='1') then
		case keyout is
			when "1110"=>
				case keyin is
					when "1110"=> data<="0000";valid<='1';
					when "1101"=> data<="0100";valid<='1';
					when "1011"=> data<="1000";valid<='1';
					when "0111"=> data<="1100";valid<='1';
					when others=> keyout<="1101";valid<='0';
				end case;
			when "1101"=>
				case keyin is
					when "1110"=> data<="0001";valid<='1';
					when "1101"=> data<="0101";valid<='1';
					when "1011"=> data<="1001";valid<='1';
					when "0111"=> data<="1101";valid<='1';
					when others=> keyout<="1011";valid<='0';
				end case;
			when "1011"=>
				case keyin is
					when "1110"=> data<="0010";valid<='1';
					when "1101"=> data<="0110";valid<='1';
					when "1011"=> data<="1010";valid<='1';
					when "0111"=> data<="1110";valid<='1';
					when others=> keyout<="0111";valid<='0';
				end case;
			when "0111"=>
				case keyin is
					when "1110"=> data<="0011";valid<='1';
					when "1101"=> data<="0111";valid<='1';
					when "1011"=> data<="1011";valid<='1';
					when "0111"=> data<="1111";valid<='1';
					when others=> keyout<="1110";valid<='0';
				end case;
			when others=>
				valid<='0';
				keyout<="1110";
		end case;
		end if;
	end process;
end behave;