📄 delay.rpt
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delay
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 05 AND2 0 2 0 1 |LPM_ADD_SUB:83|addcore:adder|:55
- 8 - B 10 DFFE + 0 3 1 1 :3
- 6 - B 10 DFFE + 0 3 0 2 s13 (:5)
- 7 - B 10 DFFE + 0 3 0 3 s12 (:6)
- 3 - B 10 DFFE + 0 3 0 4 s11 (:7)
- 4 - B 10 DFFE + 0 2 0 5 s10 (:8)
- 2 - B 10 OR2 s 1 3 0 4 ~45~1
- 1 - B 10 OR2 0 4 0 4 :68
- 5 - B 10 OR2 s 0 3 0 2 ~119~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\delay.rpt
delay
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\delay.rpt
delay
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\delay.rpt
delay
** EQUATIONS **
clk : INPUT;
sin : INPUT;
-- Node name is 'sout'
-- Equation name is 'sout', type is output
sout = _LC8_B10;
-- Node name is ':8' = 's10'
-- Equation name is 's10', location is LC4_B10, type is buried.
s10 = DFFE( _EQ001, GLOBAL(!clk), VCC, VCC, VCC);
_EQ001 = _LC1_B10 & _LC2_B10 & !s10;
-- Node name is ':7' = 's11'
-- Equation name is 's11', location is LC3_B10, type is buried.
s11 = DFFE( _EQ002, GLOBAL(!clk), VCC, VCC, VCC);
_EQ002 = _LC1_B10 & s10 & !s11
# _LC1_B10 & _LC2_B10 & !s10 & s11;
-- Node name is ':6' = 's12'
-- Equation name is 's12', location is LC7_B10, type is buried.
s12 = DFFE( _EQ003, GLOBAL(!clk), VCC, VCC, VCC);
_EQ003 = _LC5_B10 & !s10 & s12
# _LC5_B10 & !s11 & s12
# _LC5_B10 & s10 & s11 & !s12;
-- Node name is ':5' = 's13'
-- Equation name is 's13', location is LC6_B10, type is buried.
s13 = DFFE( _EQ004, GLOBAL(!clk), VCC, VCC, VCC);
_EQ004 = !_LC1_B5 & _LC5_B10 & s13
# _LC5_B10 & !s12 & s13
# _LC1_B5 & _LC5_B10 & s12 & !s13;
-- Node name is '|LPM_ADD_SUB:83|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ005);
_EQ005 = s10 & s11;
-- Node name is ':3'
-- Equation name is '_LC8_B10', type is buried
_LC8_B10 = DFFE( _EQ006, GLOBAL(!clk), VCC, VCC, VCC);
_EQ006 = !_LC2_B10 & !s10
# _LC1_B10;
-- Node name is '~45~1'
-- Equation name is '~45~1', location is LC2_B10, type is buried.
-- synthesized logic cell
_LC2_B10 = LCELL( _EQ007);
_EQ007 = s11
# s12
# s13
# !sin;
-- Node name is ':68'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ008);
_EQ008 = _LC8_B10 & !s11
# _LC8_B10 & !s13
# _LC8_B10 & !s12;
-- Node name is '~119~1'
-- Equation name is '~119~1', location is LC5_B10, type is buried.
-- synthesized logic cell
_LC5_B10 = LCELL( _EQ009);
_EQ009 = _LC1_B10 & s10
# _LC1_B10 & _LC2_B10;
Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\delay.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,539K
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