📄 antishake.rpt
字号:
- 1 - C 20 DFFE + 1 0 0 2 s11 (:12)
- 1 - A 08 DFFE + 1 0 0 2 s10 (:13)
- 3 - C 11 DFFE + 0 1 0 1 s23 (:14)
- 3 - B 05 DFFE + 0 1 0 1 s22 (:15)
- 2 - C 20 DFFE + 0 1 0 1 s21 (:16)
- 3 - A 08 DFFE + 0 1 0 1 s20 (:17)
- 1 - C 11 AND2 0 2 1 0 :120
- 2 - B 05 AND2 0 2 1 0 :121
- 4 - C 20 AND2 0 2 1 0 :122
- 2 - A 08 AND2 0 2 1 0 :123
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\antishake.rpt
antishake
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\antishake.rpt
antishake
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information:e:\documents\maple8282\my documents\study\dds\maple8282\antishake.rpt
antishake
** EQUATIONS **
clk : INPUT;
sin0 : INPUT;
sin1 : INPUT;
sin2 : INPUT;
sin3 : INPUT;
-- Node name is 'sout0'
-- Equation name is 'sout0', type is output
sout0 = _LC2_A8;
-- Node name is 'sout1'
-- Equation name is 'sout1', type is output
sout1 = _LC4_C20;
-- Node name is 'sout2'
-- Equation name is 'sout2', type is output
sout2 = _LC2_B5;
-- Node name is 'sout3'
-- Equation name is 'sout3', type is output
sout3 = _LC1_C11;
-- Node name is ':13' = 's10'
-- Equation name is 's10', location is LC1_A8, type is buried.
s10 = DFFE( sin0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':12' = 's11'
-- Equation name is 's11', location is LC1_C20, type is buried.
s11 = DFFE( sin1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':11' = 's12'
-- Equation name is 's12', location is LC1_B5, type is buried.
s12 = DFFE( sin2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':10' = 's13'
-- Equation name is 's13', location is LC2_C11, type is buried.
s13 = DFFE( sin3, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':17' = 's20'
-- Equation name is 's20', location is LC3_A8, type is buried.
s20 = DFFE( s10, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':16' = 's21'
-- Equation name is 's21', location is LC2_C20, type is buried.
s21 = DFFE( s11, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':15' = 's22'
-- Equation name is 's22', location is LC3_B5, type is buried.
s22 = DFFE( s12, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':14' = 's23'
-- Equation name is 's23', location is LC3_C11, type is buried.
s23 = DFFE( s13, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':120'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = LCELL( _EQ001);
_EQ001 = s13 & !s23;
-- Node name is ':121'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = LCELL( _EQ002);
_EQ002 = s12 & !s22;
-- Node name is ':122'
-- Equation name is '_LC4_C20', type is buried
_LC4_C20 = LCELL( _EQ003);
_EQ003 = s11 & !s21;
-- Node name is ':123'
-- Equation name is '_LC2_A8', type is buried
_LC2_A8 = LCELL( _EQ004);
_EQ004 = s10 & !s20;
Project Informatione:\documents\maple8282\my documents\study\dds\maple8282\antishake.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,671K
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