log.txt

arm控制FPGA的DDR测试代码

                                                          Log file                                                       

Generated by mig version 1.6 at 星期二 十月 17 09:21:51 2006


Reading design libraries of xc3s4000-fg900... successful !
Clearing output directory C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen successful! 
Removing C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl successful! 
Removing C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/par successful! 
Removing C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/synth successful! 
Removing C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/sim successful! 
Removing C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/docs successful! 
Removing C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb successful! 
Creating the directory C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb...successful!
Creating the directory C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/par...successful!
Creating the directory C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/docs ...successful! 
Creating the directory C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/synth ...successful! 
Creating the directory C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/sim ...successful! 
Creating the directory C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl ...successful! 

/*******************************************************/
/*			       Controller  0					           */
/*******************************************************/
Cloning Data bits  ...successful!
Cloning Strobe bits  ...successful!
Cloning Mask bits  ...successful!
Cloning Clock bits  ...successful!
Removing unwanted signal names from MT46V16M16P-75...successful!
Copying all the files from docs ...
copying c:/appls/Xilinx81/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_6/bin/nt/../../data/docs/spartan3/DDR SDRAM/768c.pdf to C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/docs ...successful!
 ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_cal_top.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_clk_dcm.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_cmd_fsm_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_path_rst.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_ddr1_test_bench_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_dqs_delay.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_fifo_0_wr_en_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_fifo_1_wr_en_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_glbl.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_infrastructure.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_infrastructure_top.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_parameters_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_rd_gray_cntr.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_s3_ddr_iob.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_s3_dqs_iob.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_wr_gray_cntr.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_parameters_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_cmp_data_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_cal_ctl_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_mybufg_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_tap_dly_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_controller_iobs_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_addr_gen_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_path_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_path_iobs_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_read_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_RAM8D_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_read_controller_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_data_write_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_ddr1_dm_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_main_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_top_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_infrastructure_iobs_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_iobs_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_lfsr32_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_controller_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_ucf_constraints_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/synth/ddr_cntl_a_script_pre_0.tcl ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a_sdc_constraints_0.v ...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/par/ddr_cntl_a.ucf
...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/par/ddr_cntl_a.ucf...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/synth/ddr_cntl_a.sdc...successful!
Generating the file C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/ddr_cntl_a.v......successful! 

Allocating pins for the signals.....

Verifying proximity rules for local clock distribution...
	Rule met... generating pinouts for set 0 to 7
Verifying proximity rules for local clock distribution...
	Rule met... generating pinouts for set 8 to 15
Verifying proximity rules for local clock distribution...
	Rule met... generating pinouts for set 16 to 23
Verifying proximity rules for local clock distribution...
	Rule met... generating pinouts for set 24 to 31


Successfully generated "DDR SDRAM" interface for controller 0.


*******************************************
Successfully generated DDR1 interface.
Look at C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/rtl/
C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/synth/
C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/docs  and
C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/par for output files.
Run the C:/user/project/avc_sp3/ise81_sp3/CoreGenModules/sp34k-fg900/coregen/ddr_cntl_a_withtb/par/ise_flow_3.bat file to create the ncd file.
Pin allocation  ...successful.

Result:
Successful