ddr_cntl_a_infrastructure_iobs_0.v

来自「arm控制FPGA的DDR测试代码」· Verilog 代码 · 共 121 行

/////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_infrastructure_iobs_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
//Device: Spartan-3/3e
//Design Name: DDR1_S3/S3e
//Description: This module contains the FDDRRSE instantiations for the clocks.
///////////////////////////////////////////////////////////////////////////////

`include "ddr_cntl_a_parameters_0.v"
`timescale 1ns/100ps

module    ddr_cntl_a_infrastructure_iobs_0   ( 
	
	DDR_CK,
	DDR_CK_N,
      clk0,              
      clk90
      );
      
input      clk0;              
input      clk90;    
output	[`clk_width-1:0]DDR_CK;
output	[`clk_width-1:0]DDR_CK_N;
  
   

		wire ddr1_clk0_q; 
		wire ddr1_clk0b_q;

		wire ddr1_clk1_q; 
		wire ddr1_clk1b_q;

wire vcc;   
wire gnd;   


assign  gnd = 1'b0;
assign  vcc = 1'b1;   





//----  Component instantiations  ----

//--- ***********************************
//---  DCI Input buffer for System clock

//---- ***********************************************************
//----     Output DDR generation
//----     This includes instantiation of the output DDR flip flop
//----     for ddr clk's and dimm clk's
//---- ***********************************************************


	
FDDRRSE DDRCLK0_INST    ( .Q  (ddr1_clk0_q), 
                          .C0 (clk0), 
                          .C1 (~clk0), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
FDDRRSE DDRCLK0B_INST    ( .Q  (ddr1_clk0b_q), 
                          .C0 (clk0), 
                          .C1 (~clk0), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );


FDDRRSE DDRCLK1_INST    ( .Q  (ddr1_clk1_q), 
                          .C0 (clk0), 
                          .C1 (~clk0), 
                          .CE (vcc), 
                          .D0 (vcc), 
                          .D1 (gnd), 
                          .R  (gnd), 
                          .S  (gnd)
                          );
FDDRRSE DDRCLK1B_INST    ( .Q  (ddr1_clk1b_q), 
                          .C0 (clk0), 
                          .C1 (~clk0), 
                          .CE (vcc), 
                          .D0 (gnd), 
                          .D1 (vcc), 
                          .R  (gnd), 
                          .S  (gnd)
                          );


//---- ******************************************
//---- Ouput BUffers for ddr clk's and dimm clk's
//---- ******************************************


	
	OBUF r0  ( .I(ddr1_clk0_q),  .O(DDR_CK[0]));
	OBUF r0b  ( .I(ddr1_clk0b_q),  .O(DDR_CK_N[0]));

	OBUF r1  ( .I(ddr1_clk1_q),  .O(DDR_CK[1]));
	OBUF r1b  ( .I(ddr1_clk1b_q),  .O(DDR_CK_N[1]));


endmodule