adr_cntrl_timingsheet_0.xls

来自「arm控制FPGA的DDR测试代码」· XLS 代码 · 共 12 行

Uncertainity parameter                       	Value                                  	Uncertainity before DQS             	Uncertainity after DQS              	Meaning
Tclock                                       	7518.80                               	                                        	                                        	clock period
Memory address and control input setup time  	900                                  	900                               	0                               	
Memory address and control input hold time   	900                                  	0                               	900                               	
Tpackage_skew                                	90                               	45                        	45                        	Package skew
Clock jitter                                 	0                                  	0                               	0                               	Same DCM is used to generate DQ and DQS
Clock_tree_skew                              	25                                	25                         	25                         	Small value considered for skew on global clock line since detection of DQS and associated DQ are placed close to each other
Tclock_out_phase                             	140                                	140                         	140                         	Phase offset error between different clock outputs of the same DCM
Pcb_layout_skew                              	400                               	400                        	400                        	Skew between data lines and asociated strobe on the board
Data valid window - min/max                  	5063.80                    	1510.00             	1510.00             	Valid data window
Margin                                       	4498.80