ddr_cntl_a_data_path_iobs_0.v

arm控制FPGA的DDR测试代码

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  / Vendor: Xilinx
// \   \   \/ Version: 1.6
//  \   \    Application : MIG
//  /   /    Filename: ddr_cntl_a_data_path_iobs_0.v
// /___/   /\ Date Last Modified:  Tue Jul 11 2006
// \   \  /  \ Date Created: Mon May 2 2005
//  \___\/\___\
// Device: Spartan-3/3e
// Design Name: DDR1_S3/S3e
// Description: This module contains the instantiations for
//			-s3_ddr_iob,
//			-s3_dqs_iob and
//			-ddr_dm modules
///////////////////////////////////////////////////////////////////////////////

`include "../rtl/ddr_cntl_a_parameters_0.v"

`timescale 1ns/100ps
module ddr_cntl_a_data_path_iobs_0 (

    clk,               
    clk90,         
    reset90_r,         
    dqs_reset,         
    dqs_enable,        
    ddr_dqs,           
    ddr_dq,            
    write_data_falling,
    write_data_rising, 
    write_en_val,
    write_en_val1,      
    data_mask_f,       
    data_mask_r,
    

	dqs_int_delay_in0,

	dqs_int_delay_in1,

	dqs_int_delay_in2,

	dqs_int_delay_in3,
			ddr_dm   ,

    ddr_dq_val         
               
);

input    clk;             
input	 clk90; 
//input    clk180;             
//input	 clk270;                      
input    reset90_r;       
input	 dqs_reset;         
input    dqs_enable;        
inout    [(`data_strobe_width-1):0]ddr_dqs;          
inout    [(`data_width-1):0]ddr_dq;          
input	 [(`data_width-1):0]write_data_falling;
input    [(`data_width-1):0]write_data_rising; 
input    write_en_val;  
input    write_en_val1;    
input    [(`data_mask_width-1):0]data_mask_f;   
input    [(`data_mask_width-1):0]data_mask_r;   

	output    dqs_int_delay_in0; 

	output    dqs_int_delay_in1; 

	output    dqs_int_delay_in2; 

	output    dqs_int_delay_in3; 
output    [(`data_width-1):0]ddr_dq_val;
		output     [((`data_mask_width)-1):0]ddr_dm; 




wire [(`data_width-1):0]ddr_dq_in;


assign ddr_dq_val = ddr_dq_in;

 ddr_cntl_a_ddr1_dm_0 ddr1_dm0   (
                             .ddr_dm       (ddr_dm),
                             .mask_falling (data_mask_f),
                             .mask_rising  (data_mask_r),
                             .clk90        (clk90)
                            // .clk270       (clk270)
                            );



//***********************************************************************
//    Read Data Capture Module Instantiations
//***********************************************************************
// DQS IOB instantiations
//***********************************************************************


  ddr_cntl_a_s3_dqs_iob  s3_dqs_iob0 (
                              .clk            (clk),
                             // .clk180         (clk180),
                              .ddr_dqs_reset  (dqs_reset),
                              .ddr_dqs_enable (dqs_enable),
                              .ddr_dqs        (ddr_dqs[0]),
                              .dqs            (dqs_int_delay_in0)
			    );



  ddr_cntl_a_s3_dqs_iob  s3_dqs_iob1 (
                              .clk            (clk),
                             // .clk180         (clk180),
                              .ddr_dqs_reset  (dqs_reset),
                              .ddr_dqs_enable (dqs_enable),
                              .ddr_dqs        (ddr_dqs[1]),
                              .dqs            (dqs_int_delay_in1)
			    );



  ddr_cntl_a_s3_dqs_iob  s3_dqs_iob2 (
                              .clk            (clk),
                             // .clk180         (clk180),
                              .ddr_dqs_reset  (dqs_reset),
                              .ddr_dqs_enable (dqs_enable),
                              .ddr_dqs        (ddr_dqs[2]),
                              .dqs            (dqs_int_delay_in2)
			    );



  ddr_cntl_a_s3_dqs_iob  s3_dqs_iob3 (
                              .clk            (clk),
                             // .clk180         (clk180),
                              .ddr_dqs_reset  (dqs_reset),
                              .ddr_dqs_enable (dqs_enable),
                              .ddr_dqs        (ddr_dqs[3]),
                              .dqs            (dqs_int_delay_in3)
			    );


	


//******************************************************************************************************************************
// DDR Data bit instantiations (72-bits)
//******************************************************************************************************************************            
 

 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob0 
				(
      				.ddr_dq_inout       (ddr_dq[0]), 
      				.write_data_falling (write_data_falling[0]), 
      				.write_data_rising  (write_data_rising[0]),
      				.read_data_in       (ddr_dq_in[0]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob1 
				(
      				.ddr_dq_inout       (ddr_dq[1]), 
      				.write_data_falling (write_data_falling[1]), 
      				.write_data_rising  (write_data_rising[1]),
      				.read_data_in       (ddr_dq_in[1]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob2 
				(
      				.ddr_dq_inout       (ddr_dq[2]), 
      				.write_data_falling (write_data_falling[2]), 
      				.write_data_rising  (write_data_rising[2]),
      				.read_data_in       (ddr_dq_in[2]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob3 
				(
      				.ddr_dq_inout       (ddr_dq[3]), 
      				.write_data_falling (write_data_falling[3]), 
      				.write_data_rising  (write_data_rising[3]),
      				.read_data_in       (ddr_dq_in[3]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob4 
				(
      				.ddr_dq_inout       (ddr_dq[4]), 
      				.write_data_falling (write_data_falling[4]), 
      				.write_data_rising  (write_data_rising[4]),
      				.read_data_in       (ddr_dq_in[4]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob5 
				(
      				.ddr_dq_inout       (ddr_dq[5]), 
      				.write_data_falling (write_data_falling[5]), 
      				.write_data_rising  (write_data_rising[5]),
      				.read_data_in       (ddr_dq_in[5]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob6 
				(
      				.ddr_dq_inout       (ddr_dq[6]), 
      				.write_data_falling (write_data_falling[6]), 
      				.write_data_rising  (write_data_rising[6]),
      				.read_data_in       (ddr_dq_in[6]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob7 
				(
      				.ddr_dq_inout       (ddr_dq[7]), 
      				.write_data_falling (write_data_falling[7]), 
      				.write_data_rising  (write_data_rising[7]),
      				.read_data_in       (ddr_dq_in[7]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob8 
				(
      				.ddr_dq_inout       (ddr_dq[8]), 
      				.write_data_falling (write_data_falling[8]), 
      				.write_data_rising  (write_data_rising[8]),
      				.read_data_in       (ddr_dq_in[8]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob9 
				(
      				.ddr_dq_inout       (ddr_dq[9]), 
      				.write_data_falling (write_data_falling[9]), 
      				.write_data_rising  (write_data_rising[9]),
      				.read_data_in       (ddr_dq_in[9]),
      				.clk90              (clk90),
      				//.clk270             (clk270),
      				.write_en_val       (write_en_val),
      				.reset              (reset90_r)
                );



 ddr_cntl_a_s3_ddr_iob  s3_ddr_iob10 
				(
      				.ddr_dq_inout       (ddr_dq[10]), 
      				.write_data_falling (write_data_falling[10]), 
      				.write_data_rising  (write_data_rising[10]),
      				.read_data_in       (ddr_dq_in[10]),
      				.clk90              (clk90),