leg.v

verilog hdl编写,六段流水线CPU.程序完整

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  LEG cpu core                                               ////
////                                                             ////
////  This file is part of the LEG FPGA SOC project              ////
////                                                             ////
////                                                             ////
////  To Do:                                                     ////
////   - make it smaller and faster                              ////
////   - rewrite the register file and data path                 ////
////  Author(s):                                                 ////
////      - Alex Li, [e-mail]                      ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Li datou                            ////
////                         [e-mail]              ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// ARM, the ARM Powered logo, Thumb, and StrongARM are         ////
//// registerd trademarks of ARM Limited, this core is simply    ////
//// build for fun, please do not use for commerical propose     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Date of Creation: 2006.11.28                                ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
////  Description                                                ////
////  leg core top level module.                                 ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
//// 2007.3.20: fix some bugs for load store multiple            ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

`include "leg_define.v"
//to do

module  leg(
              //data path
                d_irq,
                d_re,
                d_we,
                d_addr,
                d_datain,
                d_dataout,
                d_wait,
                d_be,
              //instr path
                i_datain,
                i_addr,
                i_read,
                i_wait,
              //system
                clk,
                rst
              );
//IO 
              //data path
input   [1:0]   d_irq;
output          d_re;
output          d_we;
output  [31:0]  d_addr;
input   [31:0]  d_datain;
output  [31:0]  d_dataout;
input           d_wait;
output  [3:0]   d_be;
              //instr path
input   [31:0]  i_datain;
output  [31:0]  i_addr;
output          i_read;
input           i_wait;
              //system
input           clk;
input           rst;
//end of port 

//registers

//------------------pipeline registers
reg     [27:0]  pc;
reg             i_read_d;
wire    [31:0]  f_inst;
reg     [31:0]  f_inst_backup;
reg     [31:0]  d_inst;
reg     [31:0]  r_inst;
reg     [31:0]  a_inst;
reg     [31:0]  w_inst;

//------------------pipeline control registers
wire            f_en;           //from previous
wire            f_valid;        //to next stage 
reg             f_stall;
wire            f_flush;

wire            d_en;
wire            d_valid;
reg             d_valid_r;
wire            d_stall;
wire            d_flush;

wire            r_en;
wire            r_valid;
reg             r_valid_r;
wire            r_stall;
wire            r_flush;

wire            a_en;
wire            a_valid;
reg             a_valid_r;
wire            a_flush;
wire            a_stall;

wire            w_en;
reg             w_valid;
wire            w_flush;
wire            w_stall;        //w will never stall
//

//pc related
wire            pc_en;
wire            pc_valid;
wire            pc_reload;
wire    [27:0]  pc_reload_value;
reg             pc_reload_r;

reg             i_read;
wire            fiq_in;
wire            irq_in;
wire            fiq_ena;
wire            irq_ena;
wire            i_cache_data_valid;
//fetch stage
wire    [3:0]   f_op_rs_pre;
wire    [3:0]   f_op_rm_pre; 
wire    [3:0]   f_op_rn_pre;
wire            f_op_ls_pre;
wire            f_op_ar_pre;
wire            f_op_s_bit_pre;
wire            f_op_i_bit_pre;
wire            f_op_p_bit_pre;
wire            f_op_rs_bit_pre;
wire            f_op_rm_valid;
wire            f_op_rs_valid;
wire            f_op_mrs_pre;
wire            f_op_shift_rrx_pre;

wire    [3:0]   f_op_rm;
wire    [3:0]   f_op_rn;
wire    [3:0]   f_op_rs;
wire    [3:0]   f_op_rd;
wire            f_op_str;
wire            f_op_decoded_br;
wire            f_op_decoded_br_l_bit;
wire    [31:0]  f_abort_inst;

//rf related
wire    [4:0]   f_op_decoded_raddra;
wire    [4:0]   f_op_decoded_raddrb;
wire    [4:0]   f_op_decoded_raddrc;

//load/store multiple instruction
reg     [3:0]   f_lsm_counter;
wire            f_op_decoded_ldm;
wire            f_op_decoded_stm;
reg     [1:0]   f_lsm_state;
reg     [1:0]   f_lsm_state_d;

wire    [31:0]  f_lsm_inst;
reg     [15:0]  f_lsm_rlist;
reg     [31:0]  f_lsm_inst_backup;
wire            f_lsm_generated_inst_valid;
wire            f_lsm_restore_rd_valid;
wire            f_lsm_load_base_addr;
reg             f_lsm_load_base_addr_r;
reg     [3:0]   f_lsm_addr_counter;
reg     [3:0]   f_lsm_addr_counter_backup;
wire            f_lsm_rout;
//decode stage

//arithmetic
wire            d_op_decoded_and;
wire            d_op_decoded_eor;
wire            d_op_decoded_sub;
wire            d_op_decoded_rsb;
wire            d_op_decoded_add;
wire            d_op_decoded_adc;
wire            d_op_decoded_sbc;
wire            d_op_decoded_rsc;
wire            d_op_decoded_tst;
wire            d_op_decoded_teq;
wire            d_op_decoded_cmp;
wire            d_op_decoded_cmn;
wire            d_op_decoded_orr;
wire            d_op_decoded_mov;
wire            d_op_decoded_bic;
wire            d_op_decoded_mvn;
wire            d_op_decoded_mul;
wire            d_op_deocded_mult_long;
wire            d_op_deocded_mult_accm;
//condition code
wire            d_op_cond_eqz;
wire            d_op_cond_nez;
wire            d_op_cond_csc;
wire            d_op_cond_ccc;
wire            d_op_cond_min;
wire            d_op_cond_pln;
wire            d_op_cond_vsv;
wire            d_op_cond_vcv;
wire            d_op_cond_hic;
wire            d_op_cond_lsc;
wire            d_op_cond_gen;
wire            d_op_cond_ltn;
wire            d_op_cond_gtz;
wire            d_op_cond_lez;
wire            d_op_cond_al; 
wire            d_op_cond_nv; 

//instruction decoding
wire    [03:00] d_op_condcode;          //4 bit
wire    [03:00] d_op_rn;                //4 bit
wire    [03:00] d_op_rd;                //4 bit
wire    [04:00] d_op_shift_amount;      //5 bit
wire    [01:00] d_op_shift;             //2 bit
wire    [03:00] d_op_rm;                //4 bit
wire    [03:00] d_op_rs;                //4 bit     
wire    [11:00] d_op_immediate_ls;      //12 bit 
wire    [03:00] d_op_opcode;            //4 bit
wire    [07:00] d_op_immd8;             //8 bit
wire    [03:00] rotate_imm;             //4 bit
wire            d_op_s_bit;
wire            d_shift_by_register; 
wire            d_write_porta_ena;
wire            d_write_portb_ena;

//load store decoding
wire            d_op_decoded_ldr;
wire            d_op_decoded_str;
wire            d_op_decoded_ar;