_primary.vhd

来自「verilog hdl编写,六段流水线CPU.程序完整」· VHDL 代码 · 共 33 行

library verilog;
use verilog.vl_types.all;
entity leg_dcache is
    generic(
        IDLE            : integer := 1;
        HIT_DETECT      : integer := 2;
        RELOAD_1        : integer := 4;
        RELOAD_2        : integer := 8
    );
    port(
        d_address       : in     vl_logic_vector(31 downto 0);
        d_wait          : out    vl_logic;
        d_re            : in     vl_logic;
        d_we            : in     vl_logic;
        d_datain        : in     vl_logic_vector(31 downto 0);
        d_dataout       : out    vl_logic_vector(31 downto 0);
        d_be            : in     vl_logic_vector(3 downto 0);
        dc_control      : in     vl_logic;
        ADR_O           : out    vl_logic_vector(31 downto 0);
        DAT_I           : in     vl_logic_vector(31 downto 0);
        DAT_O           : out    vl_logic_vector(31 downto 0);
        STB_O           : out    vl_logic;
        CYC_O           : out    vl_logic;
        ACK_I           : in     vl_logic;
        SEL_O           : out    vl_logic_vector(3 downto 0);
        TGD_I           : in     vl_logic_vector(3 downto 0);
        TGD_O           : out    vl_logic_vector(3 downto 0);
        WE_O            : out    vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end leg_dcache;