_primary.vhd

来自「verilog hdl编写,六段流水线CPU.程序完整」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity leg_mult is
    port(
        clk             : in     vl_logic;
        dataa           : in     vl_logic_vector(31 downto 0);
        datab           : in     vl_logic_vector(31 downto 0);
        rst             : in     vl_logic;
        r_en            : in     vl_logic;
        a_en            : in     vl_logic;
        result_low      : out    vl_logic_vector(31 downto 0);
        result_high     : out    vl_logic_vector(31 downto 0)
    );
end leg_mult;