leg.v

来自「verilog hdl编写,六段流水线CPU.程序完整」· Verilog 代码 · 共 1,311 行 · 第 1/5 页

wire            d_op_decoded_ls_b_or_w;         //byte or word indicate
wire            d_op_decoded_ls_u;              // u bit 
wire            d_op_decoded_ls_p;              // update rn
wire            d_op_decoded_ls_pre_addr;
//branch and link
reg     [27:0]  d_link_addr;
reg     [4:0]   rf_raddra_r;
wire            d_op_decoded_br;
wire    [31:0]  d_op_decoded_addr_ext;
wire            d_op_decoded_br_l_bit;
wire            d_ar_load_r15;

//software interrupt
wire            d_op_decoded_swi;
wire            d_op_decoded_undefined;
//stall condition
wire            d_ls_stall_drd_eq_frs;  //d_ls_stall_drd_eq_frs: current read address rs or rm == last load rd ------------- cause 2 cycle stall
wire            d_ls_stall_drn_eq_frs;  //d_ls_stall_drn_eq_frs: current read address rs or rm == last ls post write rn ---- cause 1 cycle stall
wire            d_ls_stall_drd_eq_frn;  //d_ls_stall_drd_eq_frn: current read address rn  == last load  rd ----------------- cause 1 cycle stall
wire            d_ar_stall_drd_eq_frs;  //d_ar_stall_drd_eq_frs: current read address rs or rm == last write rd------------- cause 1 cycle stall
wire            d_ar_stall_d_shift_and_c_wait;
//barrier shifter
wire    [31:00] shifter_result;
wire    [31:00] shifter_oprand;  
wire    [4:0]   shifter_opcode;
wire    [2:0]   shifter_mode;
wire            shifter_direction;
wire            shifter_carry_in;
wire            shifter_carry_out;
reg             shifter_carry_r;
wire            d_shifter_op_immd;
wire            d_shifter_op_logic_shiftl_by_immd;
wire            d_shifter_op_logic_shiftr_by_immd;
wire            d_shifter_op_arthm_shiftr_by_immd;
wire            d_shifter_op_rotater_by_immd;
wire            d_shifter_op_rotater_immd;

wire            d_shifter_op_logic_shiftl_by_regd;
wire            d_shifter_op_logic_shiftr_by_regd;
wire            d_shifter_op_arthm_shiftr_by_regd;
wire            d_shifter_op_rotater_by_regd;
wire            d_shifter_op_rotater_with_ext;
wire            d_op_decoded_carry_from_arithm;
//rf related
reg     [4:0]   d_op_decoded_raddrc;
wire    [4:0]   d_op_decoded_waddra;

//cpsr related
wire            d_op_decoded_msr;
wire            d_op_decoded_mrs;
wire    [7:0]   d_op_deocded_msr_mask_c;
wire    [7:0]   d_op_deocded_msr_mask_x;
wire    [7:0]   d_op_deocded_msr_mask_s;
wire    [7:0]   d_op_deocded_msr_mask_f;
wire    [31:0]  d_op_deocded_msr_mask;
wire            d_op_decoded_msr_r_bit;
wire            d_op_decoded_mrs_r_bit;
reg             d_lsm_restore_rd_valid;
reg     [3:0]   d_lsm_inst_count;
//register read stage
//arithmetic
reg             r_op_decoded_and;
reg             r_op_decoded_eor;
reg             r_op_decoded_sub;
reg             r_op_decoded_rsb;
reg             r_op_decoded_add;
reg             r_op_decoded_adc;
reg             r_op_decoded_sbc;
reg             r_op_decoded_rsc;
reg             r_op_decoded_tst;
reg             r_op_decoded_teq;
reg             r_op_decoded_cmp;
reg             r_op_decoded_cmn;
reg             r_op_decoded_orr;
reg             r_op_decoded_mov;
reg             r_op_decoded_bic;
reg             r_op_decoded_mvn;
reg             r_op_decoded_mul;
reg     [31:0]  shift_result_r;

//condition codes
reg             r_op_cond_eqz;
reg             r_op_cond_nez;
reg             r_op_cond_csc;
reg             r_op_cond_ccc;
reg             r_op_cond_min;
reg             r_op_cond_pln;
reg             r_op_cond_vsv;
reg             r_op_cond_vcv;
reg             r_op_cond_hic;
reg             r_op_cond_lsc;
reg             r_op_cond_gen;
reg             r_op_cond_ltn;
reg             r_op_cond_gtz;
reg             r_op_cond_lez;
reg             r_op_cond_al; 
reg             r_op_cond_nv; 

//r stage decoding
reg     [3:0]   r_op_rd;
reg     [3:0]   r_op_rn;
reg             r_op_decoded_ldr;
reg             r_op_decoded_str;
reg             r_op_decoded_ls_b_or_w;       //byte or word indicate
reg             r_op_decoded_ls_u;
reg             r_op_decoded_ls_p;
reg             r_op_decoded_ls_pre_addr;
reg             r_op_decoded_br;
reg     [31:0]  r_op_decoded_addr_ext;
reg             r_op_decoded_br_l_bit;
reg             r_write_porta_ena;
reg             r_write_portb_ena;
reg             r_op_decoded_ar;
wire    [4:0]   r_op_decoded_waddra;
reg             r_op_deocded_mult_accm;
reg             r_op_decoded_swi;
//control and branch
reg             r_op_s_bit;
reg     [27:0]  r_link_addr;
wire            r_exec;
wire            r_condition_passed;
wire            r_ls_stall_drd_eq_frs;
wire            r_ar_accm_stall_drd_eq_frs;
wire            r_ar_mull_stall_drh_eq_frs;
reg             r_foward_ena;
reg             r_op_decoded_carry_from_arithm;
//alu related
wire    [31:0]  r_opranda;
wire    [31:0]  r_oprandb;
wire    [31:0]  r_logic_opranda;
wire    [31:0]  r_logic_oprandb;
wire    [31:0]  r_add_sub_opranda;
wire    [31:0]  r_add_sub_oprandb;
wire            r_add_sub_carry_in;
wire            r_add_sub_carry_out;
wire            r_add_sub_overflow;
wire    [33:0]  r_add_sub_result_pre;
wire    [31:0]  r_add_sub_result;
wire            r_op_add_sub;   //1 meas add and 0 means subtraction
wire    [31:0]  r_and_result;
wire    [31:0]  r_or_result;
wire    [31:0]  r_xor_result;
wire    [31:0]  r_logic_reslut;
wire    [31:0]  r_alu_result;
reg             r_load_r15;
reg             r_lsm_restore_rd_valid;
reg     [3:0]   r_lsm_inst_count;

wire    [31:0]  mult_result_low;
wire    [31:0]  mult_result_high;
reg             r_mult_long_r;
reg 	[31:0]	mult_opranda;
reg 	[31:0]	mult_oprandb;


//a stage related
reg     [3:0]   a_op_rd;
reg     [3:0]   a_op_rn;

reg             a_write_porta_ena;
reg             a_write_portb_ena;
reg             a_op_decoded_mul;
reg             a_mult_long_r;

reg             a_op_decoded_ldr;
reg             a_op_decoded_str;
reg             a_op_decoded_ls_b_or_w;       //byte or word indicate
reg             a_op_decoded_ls_u;
reg             a_op_decoded_ls_p;
reg             a_op_decoded_ls_pre_addr;
reg     [31:0]  a_str_dataout;
reg             a_op_decoded_br;
reg             a_op_decoded_br_l_bit;
reg     [31:0]  a_op_decoded_addr_ext;
reg     [27:0]  a_link_addr;
reg             a_exec;
reg             a_condition_passed;
wire            a_br_exec;
reg             a_op_deocded_mult_accm;
reg     [31:0]  a_alu_result_r;
reg     [31:0]  a_mla_opranda_r;
//write port a decoding
wire    [4:0]   a_post_indexed_waddr;
wire    [4:0]   a_arth_waddr;
wire    [4:0]   a_link_r14;
wire            a_load_r15;
reg     [4:0]   a_op_decoded_waddra;
wire    [4:0]   a_op_decoded_waddrb;
reg             a_foward_ena;
wire    [31:0]  a_mla_result;
reg     [31:0]  a_ls_rn_data;
reg             a_irq_exec;
reg             a_lsm_restore_rd_valid;
reg     [3:0]   a_lsm_inst_count;
reg     [31:0]  a_lsm_inst_store_addr;
//w stage
reg     [3:0]   w_op_rd;
reg     [1:0]   w_low_addr;
reg     [4:0]   w_op_decoded_waddrb;
reg             w_op_decoded_ldr;
reg             w_op_decoded_str;
reg             w_op_decoded_ls_b_or_w;       //byte or word indicate
reg             w_op_decoded_ls_u;
reg             w_op_decoded_ls_p;
wire    [31:0]  w_d_shift_result;
reg             w_mult_long_r;
reg             w_op_deocded_mult_accm;
wire            w_load_r15;
reg             w_foward_ena;
reg             w_write_portb_ena;
reg     [31:0]  w_mla_result_r;
//data alignment
wire    [31:0]  w_d_lda;
wire    [31:0]  w_d_ldb;
//io related
wire            d_data_valid;

//register file related
wire    [4:0]   rf_raddra;
wire    [4:0]   rf_raddrb; 
wire    [4:0]   rf_raddrc;
wire    [31:0]  rf_rdataa;
wire    [31:0]  rf_rdatab;
wire    [31:0]  rf_rdatac;
wire    [4:0]   rf_waddra;
wire    [4:0]   rf_waddrb;
wire    [31:0]  rf_wdataa;
wire    [31:0]  rf_wdatab;
wire            rf_wea;
wire            rf_web;

//----------------cpsr and cpsr related
reg     [31:0]  cpsr;
reg     [31:0]  spsr_fiq;
reg     [31:0]  spsr_svc;
reg     [31:0]  spsr_abt;
reg     [31:0]  spsr_irq;
reg     [31:0]  spsr_und;       //it's not worth to implemented them into a m4k, so I just left them as registers
wire    [31:0]  current_spsr;

wire            cpsr_n_o;
wire            cpsr_z_o;
wire            cpsr_c_o;
wire            cpsr_v_o;
wire            cpsr_q_o;       //not implemented
wire    [18:00] cpsr_dnm_o;     //not implemented
wire            cpsr_i_o;       //irq control 1: irq disable
wire            cpsr_f_o;       //frq control 1: frq disable
wire            cpsr_t_o;       //thumb state, not implemented
wire    [04:00] cpsr_m_o;       //mode registers

wire            cpsr_n_i;
wire            cpsr_z_i;
wire            cpsr_c_i;
wire            cpsr_v_i;
wire            cpsr_q_i;       //not implemented
wire    [18:00] cpsr_dnm_i;     //not implemented
wire            cpsr_i_i;       //irq control 1: irq disable
wire            cpsr_f_i;       //frq control 1: frq disable
wire            cpsr_t_i;       //thumb state, not implemented
wire    [04:00] cpsr_m_i;       //mode registers