leg_dpram_syn.v

verilog hdl编写,六段流水线CPU.程序完整

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  LEG cpu core                                               ////
////                                                             ////
////  This file is part of the LEG FPGA SOC project              ////
////                                                             ////
////  Downloaded from:                                           ////
////     http://www.opencores.org/pdownloads.cgi/list/leg        ////
////                                                             ////
////  To Do:                                                     ////
////   - make it smaller and faster                              ////
////   - rewrite the register file and data path                 ////
////  Author(s):                                                 ////
////      - Alex Li, [e-mail]                        ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2006-2007 Alex Li                             ////
////                         [e-mail]                ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and any derivative work contains the  ////
//// original copyright notice and the associated disclaimer.    ////
////                                                             ////
//// ARM, the ARM Powered logo, Thumb, and StrongARM are         ////
//// registerd trademarks of ARM Limited, this core is simply    ////
//// build for fun, please do not use for commerical propose     ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Date of Creation: 2006.11.28                                ////
////                                                             ////
//// Version: 0.0.1                                              ////
////                                                             ////
////  Description                                                ////
////  leg core top level module.                                 ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Change log:                                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
`include "leg_define.v"
module leg_dpram_syn(
        raddr,
        rdata,
        waddr,
        wdata,
        re,
        we,
        clk,
        rst
        );
parameter       AW = 10;
parameter       DW = 32;

input   [AW-1:0]        raddr;
output  [DW-1:0]        rdata;
input   [AW-1:0]        waddr;
output  [DW-1:0]        wdata;
input                   re;
input                   we;
input                   clk;
input                   rst;

`ifdef ALTERA_CYCLONEII

`else
reg     [DW-1:0]        mem [(1<<AW)-1:0];
reg     [DW-1:0]        rdata;

//output ports
always@(posedge clk or posedge rst)
begin
        if (rst) begin
                rdata <= 32'h0;
        end
        else begin
                if (re && we)
                        rdata <= wdata;
                else if (re)
                        rdata <= mem[raddr];
        end
end

//memory contents
always@(posedge clk or posedge rst)
begin
        if (we)
                mem[waddr] <= wdata;
end

//synopsis translate off
integer i ;
initial 
begin
        for (i =0; i <(1<<(AW)); i = i+1)
                mem[i] = 32'h0;
end
//synopsis translate on
`endif

endmodule