devider.vhd

来自「用VHDL语言实现六分频」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DEVIDER IS
PORT( DOUT2 :BUFFER STD_LOGIC;
      CLK : IN STD_LOGIC );
END DEVIDER;

ARCHITECTURE BEHAVE OF DEVIDER IS
BEGIN
PROCESS(CLK)
   VARIABLE COUNT2 :INTEGER RANGE 0 TO 5 ;
   BEGIN
   IF CLK'EVENT AND CLK='1'THEN
      IF COUNT2>=0 AND COUNT2<5 THEN
         COUNT2:=COUNT2+1;
      ELSE COUNT2:=0;
           DOUT2 <= NOT DOUT2;
      END IF;
   END IF;
END PROCESS;
END ARCHITECTURE;