ddr_pll_orca_sp.v

来自「DDR RAM控制器的VHDL源码」· Verilog 代码 · 共 29 行

/* Verilog netlist generated by SCUBA ispLever_v3_Prod_Build (76c) */
/* C:\ispTOOLS30\ispFPGA\bin\nt\scuba.exe -w -n ddrpci_pll_orca -e -lang verilog -bb -type pll -arch orca4 -fin 133 -mfreq 133 -nfreq 266 -pllmode delay -tap 0 -extfb  */
/* Fri Jul 25 10:16:13 2003 */

`timescale 1 ns / 100 ps
module ddr_pll_orca_sp (clk, mclk, nclk, lock);
    input clk;
    output mclk;
    output nclk;
    output lock;

    wire nclk_t;
    wire mclk_t;

    defparam ddr_pll_orca_0_0.VCOTAP = 0;
    defparam ddr_pll_orca_0_0.NCLKMODE = "DELAY";
    defparam ddr_pll_orca_0_0.MCLKMODE = "DELAY";
    defparam ddr_pll_orca_0_0.DIV3 = 1;
    defparam ddr_pll_orca_0_0.DIV2 = 1;
    defparam ddr_pll_orca_0_0.DIV1 = 1;
    defparam ddr_pll_orca_0_0.DIV0 = 1;
    PPLL ddr_pll_orca_0_0 (.CLKIN(clk), .FB(nclk_t), .MCLK(mclk_t), 
        .NCLK(nclk_t), .LOCK(lock), .INTFB(fb));

    assign nclk = nclk_t;
    assign mclk = mclk_t;

endmodule