alu.v

来自「包含跳转」· Verilog 代码 · 共 29 行

`timescale 1ns/1ps
module ALU(ALU_O,ALU_C,C_in,op,AC_in,GR_in);
    parameter width=8;
    output ALU_C;
    output [width-1:0] ALU_O;
    input C_in;
    input [4:0] op;
    input [width-1:0] AC_in;
    input [width-1:0] GR_in;
    reg   [width-1:0] ALU_O;
    reg   ALU_C;
    always @(C_in or op or AC_in or GR_in)
    begin
        case(op)
            5'b00010:begin {ALU_C,ALU_O} = {C_in,AC_in};end
            5'b00011:begin {ALU_C,ALU_O} = {C_in,GR_in};end
            5'b00100:begin {ALU_C,ALU_O} = AC_in + GR_in;end
            5'b00101:begin {ALU_C,ALU_O} = AC_in - GR_in;end
            5'b00110:begin {ALU_C,ALU_O} = AC_in + GR_in + C_in;end
            5'b00111:begin {ALU_C,ALU_O} = AC_in + GR_in - C_in;end
            5'b01000:begin {ALU_C,ALU_O} = {C_in,AC_in&GR_in};end
            5'b01001:begin {ALU_C,ALU_O} = {C_in,AC_in^GR_in};end
            5'b01010:begin {ALU_C,ALU_O} = {GR_in,C_in};end
            5'b01011:begin {ALU_C,ALU_O} = {C_in,GR_in};end
            default:begin {ALU_C,ALU_O} = {C_in,8'b0};end
            
        endcase
    end
endmodule