spi_veriloghdl.v

本原码是基于Verilog HDL语言编写的

//cyclone: EP1C3T100C6
//maxII:  EMP570T100I5
//QUARTUS II 5.0
//MODELSIM SE 6.1B
//功能简述：接收SPI主机发来的16位数据，根据高四位值不同，返回不同的值，该值在下一次主机发送时钟信号时返回。
//SPI从机中，SCK上升沿移信数据，下降沿将要发的数据下一位移出。
module        spi16(
                        GCLK,
                        RESET_L,
                        SPI_MISO,
                        SPI_MOSI,
                        SPI_SS,
                        SPI_SCK);

        input        GCLK,RESET_L;
        input        SPI_MOSI,SPI_SS,SPI_SCK;
        output        SPI_MISO;
        
        // SPI ?à1?
        reg                [4:0] CNT_SPI;
        reg                [15:0] SHIFTER;
        reg                [15:0] DATA_TX;
        reg                [15:0] DATA_RX;
        reg                [15:0] DATA_RX_NOW;
        reg                [15:0] DATA_RX_LAST;
        reg                SPI_MISO;
        reg                SPI_SCK_LAST;
        reg                SPI_SCK_NOW;
        reg                SPI_SS_LAST;
        reg                SPI_SS_NOW;

        /****************************************/
        // spi slave 16bit 
        /****************************************/
        always        @(posedge GCLK)        //negedge RESET_L or 
                begin
                if(!RESET_L)
                        begin
                                CNT_SPI <= 5'd0;
                                SHIFTER <= 16'h00aa;
                                SPI_MISO <= 1'b0;
                        end
                else
                        begin
                                SPI_SS_LAST <= SPI_SS_NOW;
                                SPI_SS_NOW  <= SPI_SS;         //competition&adventure????
                                if((SPI_SS_LAST==1)&(SPI_SS_NOW==0))//////?????&&
                                        begin
                                                SHIFTER <= DATA_TX;
                                                SPI_MISO <= DATA_TX[15];                //???μ??,?íê×??D15
                                                CNT_SPI <= 5'd0;
                                        end
                                if(!SPI_SS)        //csó&ETH;&ETH;§
                                begin
                                        SPI_SCK_LAST <= SPI_SCK_NOW;
                                        SPI_SCK_NOW  <= SPI_SCK;
                                        if((SPI_SCK_LAST==0)&(SPI_SCK_NOW==1)&(CNT_SPI<=15))    ////?????&&
                                                begin        //posedge//ò&AElig;??
                                                        SHIFTER <= {SHIFTER[14:0],SPI_MOSI};
                                                        CNT_SPI <= CNT_SPI + 5'd1;
                                                end
                                        if((SPI_SCK_LAST==1)&(SPI_SCK_NOW==0))
                                        begin
                                                if(CNT_SPI<=15)
                                                        SPI_MISO <= SHIFTER[15];
                                                else
                                                        begin
                                                        //        THE 15th CLK, OUT '0' 
                                                        //        AND UPDATE THE DATA_RX
                                                        SPI_MISO <= 1'b0;
                                                        DATA_RX <= SHIFTER;
                                                        end 
                                                end
                                end
                        end
                end
        ///
        always        @(posedge GCLK)        //negedge RESET_L or 
                begin
                if(!RESET_L)
                        begin
                                DATA_TX <= 16'h000;
                                DATA_RX_LAST <= 16'b0;
                                DATA_RX_NOW <= 16'b0;
                        end
                else
                        begin
                        DATA_RX_LAST<= DATA_RX_NOW;
                        DATA_RX_NOW <= DATA_RX;
                        if(DATA_RX_LAST != DATA_RX_NOW)
                                begin
                                        case(DATA_RX_NOW[15:12])
                                        4'b0000:        //return 0xAA55
                                                DATA_TX <= 16'haa55;
                                        4'b0001:        //update sample rate and return it
                                                begin
                                                        DATA_TX <= 16'h1000|DATA_RX_NOW[2:0];
                                                end
                                        4'b0010:        //direct return the DATA_RX
                                                DATA_TX <= DATA_RX_NOW;
                                        endcase
                                end
                        end        
                end
endmodule

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