usb_new_pvci_cntrl_rtl.vhdl

实现USB接口功能的VHDL和verilog完整源代码

--------------------------------------------------------------------------------
--   P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--
--  Philips Electronics N.V.
--
--  Philips Semiconductors
--  Interconnectivity and Processor Peripherals group
--  Bangalore, India
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            : usb_new_pvci_cntrl_rtl.vhdl 
--
--  Module          : PVCI_CONTROLLER
--
--  Project         : VPB bus interface to USB1.1 device (USBFS22)
--
--  Author          :              
--
--  Description     : The architecture of  PVCI controller  block. This module 
--                    does address decoding.
--
--  Contact address : [e-mail]
--
---------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;

library work;
use work.PCK_APB.all;

architecture RTL of PVCI_CNTRL is
  signal Error_I:   one_bit;
begin
  
  r_data  <= Rd_data;
  Wr_data <= w_data ;  
  
  -- Grant generation
  gnt <= req;

  -- Generation of Read and Write signals for the registers in USB slave block
  -- by address decoding

  Write_Intr_Enable  <= '1' when (address(7 downto 0) = Addr_IntrEnableReg and rnw = '0'
                                  and req = '1') else '0';
  Write_Intr_Clear   <= '1' when (address(7 downto 0) = Addr_IntrClearReg and rnw = '0'
                                  and req = '1') else '0';
  Write_Intr_Set     <= '1' when (address(7 downto 0) = Addr_IntrSetReg and rnw = '0'
                                  and req = '1') else '0';
  Write_Cmd_Code     <= '1' when (address(7 downto 0) = Addr_CmdcodeReg and rnw = '0'
                                  and req = '1') else '0';
  Write_Transmt_Data <= '1' when (address(7 downto 0) = Addr_TrnsmtDataReg and rnw = '0'
                                  and req = '1') else '0';
  Write_TxPkt_Lngth  <= '1' when (address(7 downto 0) = Addr_TxPacketLengthReg and rnw = '0'
                                  and req = '1') else '0';
  Write_Usb_Cntrl    <= '1' when (address(7 downto 0) = Addr_UsbControlReg and rnw = '0'
                                  and req = '1') else '0';
  Write_Fiq_Sel      <= '1' when (address(7 downto 0) = Addr_FiqSelReg and rnw = '0'
                                  and req = '1') else '0';                                  
  Read_RxPkt_Lngth   <= '1' when (address(7 downto 0) = Addr_RxPacketLengthReg and rnw = '1'
                                  and req = '1') else '0';
  Read_Intr_Status   <= '1' when (address(7 downto 0) = Addr_IntrStatusReg and rnw = '1' 
                                  and req = '1') else '0';  
  Read_Intr_enable   <= '1' when (address(7 downto 0) = Addr_IntrEnableReg and rnw = '1'
                                  and req = '1') else '0';
  Read_Cmd_Data      <= '1' when (address(7 downto 0) = Addr_CmddataReg and rnw = '1'
                                  and req = '1') else '0';
  Read_Receive_Data  <= '1' when (address(7 downto 0) = Addr_RcvDataReg and rnw = '1'
                                  and req = '1') else '0';
  Read_Usb_Cntrl     <= '1' when (address(7 downto 0) = Addr_UsbControlReg and rnw = '1'
                                  and req = '1') else '0';
  Read_TxPkt_Lngth   <= '1' when (address(7 downto 0) = Addr_TxPacketLengthReg and rnw = '1'
                                  and req = '1') else '0';
         
  -- Error generation when the address is not correct
  Error_I <= '1' when (address(7 downto 0) > USB_MAX_ADDRESS and req = '1') else '0';
  Error   <= Error_I;
 
end RTL;