receive.v

实现USB接口功能的VHDL和verilog完整源代码

/*
# --------------------------------------------------------------------------
#    Module      : receive  
#     
#    Revision     : $Revision: 1.18 $
#    
#---------------------------------------------------------------------------
#   Purpose : Unit to receive data from card.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"

module receive	(
		// input
                mmc_enable,
//		usb_clock_uf_in,
		clock_5m,
		cs_fc_out,
		sync_reset_uf_in,
		data_cf_in,

//                start_status,
                getstatus,
                getdata,

                statuswrready_uf_in,
                endp2wrready_uf_in,
//		number_of_byte,

//		busy_in,

		// output
                statuswr_fu_out,
                statuswrdata_fu_out,
                statuswrdatadone_fu_out,

                endp2wr_fu_out,
                endp2wrdata_fu_out,
                endp2wrdatadone_fu_out,

		receive
//		busy_out
		);
	
input                   mmc_enable;
//input			usb_clock_uf_in;
input			clock_5m;
input			cs_fc_out;
input			sync_reset_uf_in;
input			data_cf_in;

//input                   start_status;
input                   getstatus;

input                   getdata;

input                   statuswrready_uf_in;
input                   endp2wrready_uf_in;

output                  statuswr_fu_out;
output  [`BYTE:`LSB]    statuswrdata_fu_out;
output                  statuswrdatadone_fu_out;

output                  endp2wr_fu_out;
output  [`BYTE:`LSB]    endp2wrdata_fu_out;
output                  endp2wrdatadone_fu_out;

output			receive;
//output			busy_out;

reg	[`BYTE:`LSB]	receive_byte;
reg	[`BYTE:`LSB]	r_byte_counter;
reg	[`FOUR:`LSB]	r_bit_counter;
reg			receive;
//reg	[`TWO:`LSB]	wr_count;
reg                     wr_fu_out;
reg     [`BYTE:`LSB]    data_fu_out;
reg                     datadone_fu_out;
reg                     check_response;
reg     [`NINE:`LSB]    timeout_count;

wire			r_transaction_done;
wire                    gen_receive;
wire                    release_receive;
wire                    start_r_bit_count;
wire                    start_wr_count;
wire                    data_temp;
wire                    ready_uf_in;
wire    [`BYTE:`LSB]    number_of_byte;
wire                    gen_response;

//assign ready_uf_in = (start_status&statuswrready_uf_in)? (start_status&statuswrready_uf_in) :
assign ready_uf_in = (getstatus&statuswrready_uf_in)? (getstatus&statuswrready_uf_in) :
                     (getdata&endp2wrready_uf_in)? (getdata&endp2wrready_uf_in): `LOW; 
//assign number_of_byte = (start_status)? `TWO:
assign number_of_byte = (getstatus)? `TWO:
                        (getdata)? `THIRTY_TWO: `ONE;
//assign statuswr_fu_out = (start_status)? wr_fu_out: `LOW;
assign statuswr_fu_out = (getstatus)? wr_fu_out: `LOW;
assign statuswrdata_fu_out = data_fu_out;
//assign statuswrdata_fu_out = (start_status)? data_fu_out: `BYTE_INITIAL_VALUE;

//always @(posedge clock_5m or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) check_response <= `LOW;
//    else if(!start_status) check_response <= start_status;
    else if(!getstatus) check_response <= getstatus;
           else if(gen_response) check_response <= gen_response;

always @(posedge clock_5m)
  if(sync_reset_uf_in) timeout_count <= `TIMEOUT_COUNT_INITIAL;
//    else if(check_response | !start_status) timeout_count <= `TIMEOUT_COUNT_INITIAL;
    else if(check_response | !getstatus) timeout_count <= `TIMEOUT_COUNT_INITIAL;
           else if(!cs_fc_out)timeout_count <= timeout_count + `HIGH;

//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
//always @(posedge usb_clock_uf_in)
//  if(sync_reset_uf_in) wr_count <= `WR_COUNT_INITIAL;
//    else if(mmc_enable & ((start_wr_count & getdata) | (start_wr_count & start_status & check_response))) wr_count <= wr_count + `HIGH;
//           else wr_count <= {`LEN_WR_COUNT{start_wr_count}};

assign start_wr_count = r_bit_counter == `GEN_WR;
assign gen_response = (((r_bit_counter == `CHECK_RESP) & (receive_byte[`LSB] ==`LOW)) | (timeout_count == `TIMEOUT_VALUE) ) & !check_response;

assign endp2wr_fu_out = (getdata)? wr_fu_out: `LOW;
assign endp2wrdata_fu_out = data_fu_out;
//assign endp2wrdata_fu_out = (getdata)? data_fu_out: `BYTE_INITIAL_VALUE;
//assign statuswrdatadone_fu_out = datadone_fu_out;
assign statuswrdatadone_fu_out = r_transaction_done;
assign endp2wrdatadone_fu_out = datadone_fu_out;

assign gen_receive = ready_uf_in &( r_bit_counter== `R_BIT_COUNT_INITIAL) & !r_transaction_done;
//assign gen_receive = ready_uf_in &( r_bit_counter== `R_BIT_COUNT_INITIAL) & !datadone_fu_out;
assign release_receive = receive & (r_bit_counter == `GEN_RELEASE);
//always @(negedge clock_5m or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) receive	<= `LOW;
    else if(gen_receive) receive <= gen_receive;
	   else if(release_receive) receive <= ~release_receive;

assign start_r_bit_count = receive | (!receive & (r_bit_counter == `LAST_RECEIVE));
//always @(posedge clock_5m or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) r_bit_counter <= `R_BIT_COUNT_INITIAL;
    else if( start_r_bit_count) r_bit_counter <= r_bit_counter - `HIGH;
           else r_bit_counter <= {`LEN_R_BIT_COUNT{start_r_bit_count}};

//always @(posedge clock_5m or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) receive_byte <= `BYTE_INITIAL_VALUE;
    else if( r_bit_counter[`FOUR] == `HIGH) 
            begin
            receive_byte <= receive_byte << `HIGH;
            receive_byte[`LSB] <= data_cf_in;
            end

assign	r_transaction_done = ( r_byte_counter == number_of_byte);

//assign data_temp = (wr_count == `WR_COUNT_TWO);
//assign data_temp = ((start_wr_count & getdata) | (start_wr_count & start_status & check_response));
assign data_temp = ((start_wr_count & getdata) | (start_wr_count & getstatus & check_response));
//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) 
    begin
    wr_fu_out <= `LOW;
    data_fu_out <= `BYTE_INITIAL_VALUE;
    end
    else
      begin
      if(mmc_enable) begin
                     wr_fu_out <= data_temp;
                     if(data_temp) data_fu_out <= receive_byte;
                     end
      end

//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
  if(sync_reset_uf_in) r_byte_counter <= `R_BYTE_COUNT_INITIAL;
    else if(mmc_enable & r_transaction_done) r_byte_counter <= {`LEN_R_BYTE_COUNT{r_transaction_done}};
           else if(mmc_enable & data_temp) r_byte_counter <= r_byte_counter + `HIGH;

//always @(posedge usb_clock_uf_in or posedge sync_reset_uf_in)
always @(posedge clock_5m)
	if(sync_reset_uf_in) datadone_fu_out <= `LOW;
	  else if(mmc_enable) datadone_fu_out <= r_transaction_done;
	
endmodule