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来自「实现USB接口功能的VHDL和verilog完整源代码」· 代码 · 共 13 行

# Reading D:/Modeltech_6.0d/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0d Apr 25 2005 
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "C:/Documents and Settings/administrator/Lb/070718.part1/070718/usb/verilog/usbmmc/gen_clock_5m.v"