data_receive.v

实现USB接口功能的VHDL和verilog完整源代码

/*
# --------------------------------------------------------------------------
#    Module      : data_receive  
#     
#    Revision     : $Revision: 1.24 $
#    
#---------------------------------------------------------------------------
#   Purpose : Unit to receive data from card.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"

module data_receive	(
		// input
                sof,
		multi_getdata,
                mmc_enable,
		data_transmit,
		setcmdwr,
		clock_5m,
		sync_reset_uf_in,
		dat_cf_in,
                spimode,
                getdata,
                divide_rate,
//                status_receive_sync,

                endp2wrready_uf_in,
                endp1rddatadone_fu_out,
                cmdrddatadone_fu_out,

		// output
                endp2wr_fu_out,
                endp2wrdata_fu_out,
                endp2wrdatadone_fu_out,
                mask_clock,
				mask_transmit,
                endp3,
//                data_receive_sync,
		data_receive
		);
input           sof;
input           setcmdwr;
input      data_transmit;
input           multi_getdata;
input           mmc_enable;
input			clock_5m;
input			sync_reset_uf_in;
input			dat_cf_in;
input                   spimode;
input                   getdata;
input    [`THREE:`LSB]  divide_rate;
//input                   status_receive_sync;

input                   endp2wrready_uf_in;
input                   cmdrddatadone_fu_out;
input                   endp1rddatadone_fu_out;

output                  endp2wr_fu_out;
output  [`BYTE:`LSB]    endp2wrdata_fu_out;
output                  endp2wrdatadone_fu_out;

//output                  data_receive_sync;
output			data_receive;
output          mask_clock;
output          mask_transmit;
output  [15:`LSB] endp3;
reg                     hold_r_bit_counter;
reg	[`BYTE:`LSB]	receive_byte;
reg	[`BYTE:`LSB]	r_byte_counter;
reg	[`FOUR:`LSB]	r_bit_counter;
//reg			data_receive;
wire            data_receive;
reg                     wr_fu_out;
reg     [`BYTE:`LSB]    data_fu_out;
reg                     datadone_fu_out;
reg                     check_response;
reg     [`SEVENTEEN:`LSB]    timeout_count;
reg     [`FIVE:`LSB]    block_count;
wire     [`FOUR:`LSB]    timeout_value;
reg                     mask_transmit;
wire                    hold_time;
wire                    rel_response;
wire                    block_count_finish;
wire			r_transaction_done;
wire                    gen_receive;
wire                    release_receive;
wire                    start_r_bit_count;
wire                    start_wr_count;
wire                    data_temp;
wire                    ready_uf_in;
wire    [`BYTE:`LSB]    number_of_byte;
wire                    gen_response;
wire                    check_time;
wire                    check_data;
wire                    check_response1;
//wire                    data_receive_sync;
reg                      tmp_data_receive;
//assign data_receive_sync = |r_bit_counter;
//assign ready_uf_in = getdata&endp2wrready_uf_in&endp1rddatadone_fu_out& !status_receive_sync; 
assign ready_uf_in = getdata&endp2wrready_uf_in&endp1rddatadone_fu_out&cmdrddatadone_fu_out; 
assign number_of_byte = `THIRTY_TWO;
//wire   mask_transmit =!check_response;
assign start_wr_count = r_bit_counter == `GEN_WR;
//assign gen_response = (r_bit_counter == `CHECK_RESP) & (receive_byte[`LSB] ==`LOW) & !check_response;
assign check_time = (r_bit_counter == `CHECK_RESP);
assign hold_time = (r_bit_counter == `HOLD_RESP);
assign check_data = (receive_byte[`LSB] ==`LOW);
assign check_response1 = (check_time & check_data);
//assign gen_response = ( !spimode & (check_response1 | (timeout_count[`SEVENTEEN:`FIFTEEN] == timeout_value) ) & !check_response );

//assign gen_response = ( !spimode & (check_response1 | (timeout_count[`SEVENTEEN:`FIFTEEN] == 3'b001) ) & !check_response );
wire   timeout_condition;
assign gen_response = ( !spimode & (check_response1 | timeout_condition ) & !check_response );
wire   timeout_error;
assign timeout_error = ( !spimode & timeout_condition );
//assign timeout_value = (spimode)? `TIMEOUT_VALUE_SPI : `TIMEOUT_VALUE_MMC;
//assign timeout_condition = (setcmdwr)? (timeout_count[`FIVE] & timeout_count[`FOUR] & !timeout_count[`LSB]) : (timeout_count[`SEVENTEEN:`FIFTEEN] == timeout_value);
assign timeout_condition = (setcmdwr)? (timeout_count[8] & !timeout_count[0]) : ({timeout_count[`SEVENTEEN:`FIFTEEN],timeout_count[`LSB]} == timeout_value);
assign timeout_value = 4'b1110;  // 24MHz
/*
always @(divide_rate)
  begin
    case(divide_rate)
      3'b011 : timeout_value = 3'b111;  // 24MHz
      3'b010 : timeout_value = 3'b111;  // 12MHz
      3'b001 : timeout_value = 3'b010;  // 6MH
      default : timeout_value = 3'b111; // 24MHz
    endcase
  end
*/
reg [1:0] fifo_wr_count;

always @(posedge clock_5m)
 if(sync_reset_uf_in || !multi_getdata)
	fifo_wr_count <= 'h0;
 else if(setcmdwr)
	fifo_wr_count <= (wr_fu_out) ? fifo_wr_count +1'b1 : fifo_wr_count;

wire mask_wr_fu_out = (fifo_wr_count =='h2 ) ? 1'b0 : 1'b1;
assign endp2wr_fu_out = wr_fu_out &&  mask_wr_fu_out;
assign endp2wrdata_fu_out = data_fu_out;
//assign endp2wr_fu_out = wr_fu_out;
assign endp2wrdatadone_fu_out = datadone_fu_out;

assign gen_receive = ready_uf_in &( r_bit_counter== `R_BIT_COUNT_INITIAL) & !r_transaction_done;
assign release_receive = tmp_data_receive & (r_bit_counter == `GEN_RELEASE);
always @(posedge clock_5m)
  if(sync_reset_uf_in| !getdata) timeout_count <= `TIMEOUT_COUNT_INITIAL;
    else if( check_response | !getdata |spimode) timeout_count <= `TIMEOUT_COUNT_INITIAL;
           else if(tmp_data_receive)timeout_count <= timeout_count + `HIGH;
                  else timeout_count <= timeout_count;

assign rel_response = !getdata | block_count_finish;
reg   [`BYTE:`LSB]  timeout_err_count;
always @(posedge clock_5m)
  if(sync_reset_uf_in|!setcmdwr) timeout_err_count <= `TIMEOUT_ERR_COUNT_INITIAL;
    else if(timeout_error) timeout_err_count <= timeout_err_count + `HIGH;
           else timeout_err_count <= timeout_err_count;

always @(posedge clock_5m)
  if(sync_reset_uf_in) check_response <= `LOW;
    else if(spimode) check_response <= spimode;
           else if(!getdata | block_count_finish) check_response <= !rel_response;
                  else if(gen_response) check_response <= gen_response;
                         else check_response <= check_response;
//wire mask_clock = (block_count == 'h0f && r_byte_counter != 'hff && r_byte_counter != 'h00 ) ? 1'b1: 1'b0;
//wire mask_clock = (( !block_count[4] & &block_count[3:0] == `HIGH) && (&r_byte_counter != `HIGH) && (|r_byte_counter != `LOW) ) ? 1'b1: 1'b0;
wire mask_clock = (( !block_count[4] & &block_count[3:0] == `HIGH) && (!r_byte_counter[5]) && (|r_byte_counter[4:0]) ) ? 1'b1: 1'b0;
assign block_count_finish = block_count == `SEVENTEEN;
always @(posedge clock_5m) // 512 +32 count
  if(sync_reset_uf_in) block_count <= `BLOCK_COUNT_INITIAL;
    //else if(!getdata | block_count_finish ) block_count <= `BLOCK_COUNT_INITIAL;
    else if(!getdata | block_count_finish | data_transmit) block_count <= `BLOCK_COUNT_INITIAL;
           else if((datadone_fu_out & !multi_getdata)|(datadone_fu_out & multi_getdata & (&block_count))) block_count <= block_count + `HIGH;
                  else block_count <= block_count;

always @(posedge clock_5m)
  if(sync_reset_uf_in|!getdata) tmp_data_receive	<= `LOW;
    else if(!datadone_fu_out & gen_receive) tmp_data_receive <= gen_receive;
	   else if(release_receive) tmp_data_receive <= ~release_receive;
                  else tmp_data_receive <= tmp_data_receive;

assign data_receive =  tmp_data_receive;
//assign data_receive = (setcmdwr) ? getdata && tmp_data_receive : 
//                      (!getdata) ? tmp_data_receive : 

assign start_r_bit_count = tmp_data_receive | (!tmp_data_receive & (r_bit_counter == `LAST_RECEIVE));
always @(posedge clock_5m)
  if(sync_reset_uf_in|!getdata ) 
    begin
    r_bit_counter <= `R_BIT_COUNT_INITIAL;
    hold_r_bit_counter <= `LOW;
    end
    else if(!spimode)
           begin  // check time --> check start bit ,hold time  sttart bit甫 力芭 窍扁 困秦 count甫
				  // 老矫 沥瘤
             if( start_r_bit_count )
                begin
                if(!check_time & !hold_time) r_bit_counter <= r_bit_counter - `HIGH;
                  else if(!check_response)
                         begin
                           hold_r_bit_counter <= `LOW;
                           if(check_response1) r_bit_counter <= r_bit_counter - `HIGH;
                             else r_bit_counter <= r_bit_counter;
                         end
                         else if(!hold_r_bit_counter) hold_r_bit_counter <= `HIGH;
                                else r_bit_counter <= r_bit_counter - `HIGH;
                end
               else r_bit_counter <= {`LEN_R_BIT_COUNT{start_r_bit_count}};
           end
           else
             begin
               if( start_r_bit_count) r_bit_counter <= r_bit_counter - `HIGH;
                 else r_bit_counter <= {`LEN_R_BIT_COUNT{start_r_bit_count}};
             end

always @(posedge clock_5m)
  if(sync_reset_uf_in) receive_byte <= `BYTE_INITIAL_VALUE;
    else if( r_bit_counter[`FOUR] == `HIGH) 
            begin
            receive_byte <= receive_byte << `HIGH;
            receive_byte[`LSB] <= dat_cf_in;
            end
            else begin
                 receive_byte <= receive_byte;
                 end

assign	r_transaction_done = ( r_byte_counter == number_of_byte);
assign data_temp = (start_wr_count & check_response);
//assign data_temp = (start_wr_count & getdata);

always @(posedge clock_5m)
  if(sync_reset_uf_in) 
    begin
    wr_fu_out <= `LOW;
    data_fu_out <= `BYTE_INITIAL_VALUE;
    end
    else
      begin
      if(mmc_enable& !setcmdwr) //just two byte latch
//					 wr_fu_out <= (receive_byte != 'h00 || !setcmdwr) ? 
//					                data_temp : wr_fu_out;
//					 if(data_temp && (receive_byte != 'h00 || !setcmdwr))
//							 data_fu_out <= receive_byte;
        begin
        wr_fu_out <=data_temp;
        if(data_temp) data_fu_out <= receive_byte;
        end
        else begin
             wr_fu_out <= wr_fu_out;
             data_fu_out <= data_fu_out;
             end
      end
reg  [6:0]  busy_count;
always@(posedge clock_5m)
   if(sync_reset_uf_in|!getdata) 
     begin
     mask_transmit <= `HIGH;
     busy_count <= 'b000_0000;
     end
     else if(mmc_enable && data_temp && setcmdwr & mask_transmit) 
            begin
            mask_transmit <= `LOW ;
            busy_count <= busy_count;
            end
            else 
              begin
              if(sof& !mask_transmit) busy_count <= busy_count + `HIGH; 
                else if(busy_count[6] == 1'b1) busy_count <= 'b000_0000;
                       else busy_count <= busy_count;
              if( (receive_byte[`LSB] & !((r_bit_counter== 'h0)|(r_bit_counter == 'hf))) | (busy_count[6] == 1'b1) ) mask_transmit <= `HIGH;
                else mask_transmit <= mask_transmit;					
              end
reg  [3:`LSB]  busy_err_count;
always@(posedge clock_5m)
   if(sync_reset_uf_in|!setcmdwr) busy_err_count <= 4'b0000;
     else if(busy_count[6] == 1'b1) busy_err_count <= busy_err_count + `HIGH;
            else busy_err_count <= busy_err_count;

reg   [3:`LSB] crc_error_count;
always@(posedge clock_5m)
   if(sync_reset_uf_in|!setcmdwr) crc_error_count <= 4'b0000;
     else if(mmc_enable & (&r_byte_counter) & (r_bit_counter == 'hc) & block_count[`FIVE])
             case(receive_byte[2:0])
               3'b010 : crc_error_count <= crc_error_count;
               default : crc_error_count <= crc_error_count + `HIGH;
             endcase
             else
               crc_error_count <= crc_error_count; 

always @(posedge clock_5m)
  if(sync_reset_uf_in | !getdata) r_byte_counter <= `R_BYTE_COUNT_INITIAL;
    else if(mmc_enable & r_transaction_done) r_byte_counter <= {`LEN_R_BYTE_COUNT{r_transaction_done}};
           else if(mmc_enable & data_temp) r_byte_counter <= r_byte_counter + `HIGH;
			 else r_byte_counter <= r_byte_counter;

assign                   endp3 = { timeout_err_count, crc_error_count, busy_err_count };

always @(posedge clock_5m)
	if(sync_reset_uf_in) datadone_fu_out <= `LOW;
	  else if(mmc_enable) datadone_fu_out <= r_transaction_done;
                 else datadone_fu_out <= datadone_fu_out;
	
endmodule