status_receive.v

实现USB接口功能的VHDL和verilog完整源代码

/*
# --------------------------------------------------------------------------
#    Module      : status_receive  
#     
#    Revision     : $Revision: 1.28 $
#    
#---------------------------------------------------------------------------
#   Purpose : Unit to receive data from card.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"

module status_receive	(
		// input
                tmp_multi_getdata,
                mmc_enable,
		clock_5m,
		sync_reset_uf_in,
		status_cf_in,
                dat_cf_in,
                spimode,
                sof,

                getstatus_in,
                getstatus_check,
                statuswrready_uf_in,
                cmdrddatadone_fu_out,

		// output
                statuswr_fu_out,
                statuswrdata_fu_out,
                statuswrdatadone_fu_out,

                busy_end_out,
                status_busy_check,
		status_receive
		);
	
input                   tmp_multi_getdata;
input                   mmc_enable;
input			clock_5m;
input			sync_reset_uf_in;
input                   dat_cf_in;
input			status_cf_in;
input                   spimode;
input                   sof;

input                   getstatus_in;
input                   getstatus_check;
input                   statuswrready_uf_in;
input                   cmdrddatadone_fu_out;

output                  statuswr_fu_out;
output  [`BYTE:`LSB]    statuswrdata_fu_out;
output                  statuswrdatadone_fu_out;

output			status_receive;
output                  busy_end_out;
output                  status_busy_check;

reg	[`BYTE:`LSB]	receive_byte;
reg	[`BYTE:`LSB]	r_byte_counter;
reg	[`FOUR:`LSB]	r_bit_counter;
reg			status_receive;
reg                     wr_fu_out;
reg     [`BYTE:`LSB]    data_fu_out;
reg                     datadone_fu_out;
reg                     check_response;
reg     [`NINE:`LSB]    timeout_count;

wire			r_transaction_done;
wire                    gen_receive;
wire                    release_receive;
wire                    start_r_bit_count;
wire                    start_wr_count;
wire                    data_temp;
wire                    ready_uf_in;
wire    [`BYTE:`LSB]    number_of_byte;
wire                    gen_response;
wire                    check_time;
wire                    check_data;
wire                    check_response1;
//wire    [`BYTE:`LSB]    timeout_value;
wire                    timeout_value;

reg                     tmp_multi_getdata1;
reg                     tmp_multi_getdata2;
reg                     busy_end;

always @(posedge clock_5m)
  begin
  tmp_multi_getdata1 <= tmp_multi_getdata;
  tmp_multi_getdata2 <= tmp_multi_getdata1;
  end
wire getstatus = getstatus_in | getstatus_check;
assign ready_uf_in = getstatus &statuswrready_uf_in&cmdrddatadone_fu_out& !tmp_multi_getdata2;
//assign number_of_byte = (spimode)? `THREE : `SEVEN;
assign number_of_byte = `SEVEN;
assign statuswr_fu_out = wr_fu_out;
assign statuswrdata_fu_out = data_fu_out;

always @(posedge clock_5m)
  if(sync_reset_uf_in) check_response <= `LOW;
    else if(!getstatus) check_response <= getstatus;
           else if(gen_response) check_response <= gen_response;
                  else check_response <= check_response;

always @(posedge clock_5m)
  if(sync_reset_uf_in) timeout_count <= `TIMEOUT_COUNT_INITIAL;
    else if(check_response | !getstatus) timeout_count <= `TIMEOUT_COUNT_INITIAL;
           else if(status_receive)timeout_count <= timeout_count + `HIGH;
                  else timeout_count <= timeout_count;

assign start_wr_count = r_bit_counter == `GEN_WR;
assign check_time = (r_bit_counter == `CHECK_RESP);
assign check_data = (receive_byte[`LSB] ==`LOW);
assign check_response1 = (check_time & check_data);
//assign timeout_value = (spimode)? `TIMEOUT_VALUE_SPI : `TIMEOUT_VALUE_MMC;
assign timeout_value = (spimode)? 1'b1 : 1'b0;
assign gen_response = (check_response1 | (timeout_count == {4'b1010,timeout_value,3'b000} )) & !check_response;

assign statuswrdatadone_fu_out = r_transaction_done;
assign gen_receive = ready_uf_in &( r_bit_counter== `R_BIT_COUNT_INITIAL) & !r_transaction_done;
assign release_receive = status_receive & (r_bit_counter == `GEN_RELEASE);

always @(posedge clock_5m)
  if(sync_reset_uf_in) status_receive <= `LOW;
    else if(gen_receive & !datadone_fu_out) status_receive <= gen_receive;
	   else if(release_receive) status_receive <= ~release_receive;
                  else status_receive <= status_receive;

assign start_r_bit_count = status_receive | (!status_receive & (r_bit_counter == `LAST_RECEIVE));

always @(posedge clock_5m)
  if(sync_reset_uf_in) r_bit_counter <= `R_BIT_COUNT_INITIAL;
    else if(!spimode)
           begin 
             if( start_r_bit_count )
                begin
                if(!check_time) r_bit_counter <= r_bit_counter - `HIGH;
                  else if(!check_response) 
                         begin
                           if(check_response1) r_bit_counter <= r_bit_counter - `HIGH;
                             else r_bit_counter <= r_bit_counter;
                         end
                         else r_bit_counter <= r_bit_counter - `HIGH;
                end
               else r_bit_counter <= {`LEN_R_BIT_COUNT{start_r_bit_count}};
           end
           else
             begin
               if( start_r_bit_count) r_bit_counter <= r_bit_counter - `HIGH;
                 else r_bit_counter <= {`LEN_R_BIT_COUNT{start_r_bit_count}};
             end

always @(posedge clock_5m)
  if(sync_reset_uf_in) receive_byte <= `BYTE_INITIAL_VALUE;
    else if( r_bit_counter[`FOUR] == `HIGH) 
            begin
            receive_byte <= receive_byte << `HIGH;
            receive_byte[`LSB] <= status_cf_in;
            end
            else receive_byte <= receive_byte;

assign	r_transaction_done = ( r_byte_counter == number_of_byte);

assign data_temp = (start_wr_count & check_response);

always @(posedge clock_5m)
  if(sync_reset_uf_in) 
    begin
    wr_fu_out <= `LOW;
    data_fu_out <= `BYTE_INITIAL_VALUE;
    end
    else
      begin
      if(mmc_enable) begin
                     wr_fu_out <= data_temp;
                     if(data_temp) data_fu_out <= receive_byte;
                       else data_fu_out <= data_fu_out;
                     end
        else begin
             wr_fu_out <= wr_fu_out;
             data_fu_out <= data_fu_out;
             end
      end

always @(posedge clock_5m)
  if(sync_reset_uf_in) r_byte_counter <= `R_BYTE_COUNT_INITIAL;
    else if(mmc_enable & r_transaction_done) r_byte_counter <= {`LEN_R_BYTE_COUNT{r_transaction_done}};
           else if(mmc_enable & data_temp) r_byte_counter <= r_byte_counter + `HIGH;
                  else r_byte_counter <= r_byte_counter;

always @(posedge clock_5m)
	if(sync_reset_uf_in) datadone_fu_out <= `LOW;
	  else if(mmc_enable) datadone_fu_out <= r_transaction_done;
                 else datadone_fu_out <= datadone_fu_out;

reg status_busy_check;
reg status_busy_check1;
always @(posedge clock_5m)
  if(sync_reset_uf_in|spimode|!getstatus_check) status_busy_check <= `LOW;
    else if(statuswrdatadone_fu_out) status_busy_check <= `HIGH;
           else if(busy_end) status_busy_check <= `LOW;
                  else status_busy_check <= status_busy_check;
	
always @(posedge clock_5m)
  status_busy_check1 <= status_busy_check;

reg [4:0] busy_end_count;
always @(posedge clock_5m)
  if(status_busy_check1 & !spimode) 
    if(dat_cf_in | (&busy_end_count[4:2])) busy_end <= `HIGH;
       else 
         begin
         if(sof) busy_end_count <= busy_end_count + `HIGH;
           else busy_end_count <= busy_end_count;
         busy_end <= `LOW;
         end
    else 
      begin
      busy_end_count <= 5'b0_0000;
      busy_end <= `LOW;
      end

reg busy_end_out1;
always @(posedge clock_5m)
   if(!getstatus_check) busy_end_out1 <= `LOW;
     else if(busy_end) busy_end_out1 <= `HIGH;
wire busy_end_out = (getstatus_check)? busy_end_out1: `HIGH;

endmodule