usbmmc_box.v

实现USB接口功能的VHDL和verilog完整源代码

/*
# --------------------------------------------------------------------------
#    Module      : usbmmc 
#     
#    Revision     : $Revision: 1.3 $
#    
#---------------------------------------------------------------------------
#   Purpose : USB to MMC interface.
#-------------------------------------------------------------------------
*/

`include "usbmmc_variable.v"


module usbmmc_box	(
		// input
		usb_48_clock_uf_in,
                divide_rate,
		usb_clock_uf_in,
		sof,
		busy_end_out,
		setcmdwr,
		data_in,
                mmc_enable,
                disablebus,
		sync_reset_uf_in,
                spimode,
		dataout_dat_in,
		dataout_dat_out,
		dataout_dat_enable,
                getstatus,
                getdata,
                cs1_in,
                cs2_in,
                clock_5m,

		cmdrdready_uf_in,
		cmdrddata_uf_in,

		endp1rdready_uf_in,
		endp1rddata_uf_in,
		
                statuswrready_uf_in,
		endp2wrready_uf_in,

		// output
                clock_5m_out,
		cmdrd_fu_out,
                cmdrddatadone_fu_out,

		statuswr_fu_out,
		statuswrdata_fu_out,
                statuswrdatadone_fu_out,

		endp1rd_fu_out,
		endp1rddatadone_fu_out,

		endp2wr_fu_out,
		endp2wrdata_fu_out,
		endp2wrdatadone_fu_out,

        clk_mcu,
        data_out,
        endp3,
		cs1_rsv,
		cs2_rsv,
		clock_fc_out,
		datain_cmd_in,
		datain_cmd_out,
		datain_cmd_enable,
                sync_reset_made
		);
	
//	hardware structure
//	usb core(u) - mmc interface(f) - mmc card(c)
//	signal from usb core to mmc interface "_uf"
//	signal to usb core from mmc interface "_fu"
//	signal from mmc interface to mmc card "_fc"
//	signal to mmc interface from mmc card "_cf"

// variable notation : 	variable's postfix of input to usbmmc "_in"
//			variable's postfix of output from usbmmc "_out"			
// 			

input			usb_48_clock_uf_in;
input    [`THREE:`LSB]  divide_rate;
input			usb_clock_uf_in;
input                   mmc_enable;
input                   disablebus;
input			sync_reset_uf_in;
input                   spimode;
input sof;
output busy_end_out ;
input		setcmdwr;
input		data_in;

input			dataout_dat_in;
input                   getstatus;
input                   getdata;
input                   cs1_in;
input                   cs2_in;

input			cmdrdready_uf_in;
input	[`BYTE:`LSB]	cmdrddata_uf_in;

input			endp1rdready_uf_in;
input	[`BYTE:`LSB]	endp1rddata_uf_in;

input                   statuswrready_uf_in;
input			endp2wrready_uf_in;
input           clock_5m;
input			datain_cmd_in;

output                  cs1_rsv;
output                  cs2_rsv;
output                  clock_5m_out;
output			cmdrd_fu_out;
output			cmdrddatadone_fu_out;
output			dataout_dat_out;
output			dataout_dat_enable;

output			statuswr_fu_out;
output	[`BYTE:`LSB]	statuswrdata_fu_out;
output			statuswrdatadone_fu_out;

output			endp1rd_fu_out;
output			endp1rddatadone_fu_out;

output			endp2wr_fu_out;
output	[`BYTE:`LSB]	endp2wrdata_fu_out;
output			endp2wrdatadone_fu_out;

output			clock_fc_out;
output			datain_cmd_out;
output			datain_cmd_enable;

output			sync_reset_made;
output          data_out ;
output          clk_mcu ;
output   [15:`LSB]       endp3 ;
wire     [15:`LSB]       endp3 = 16'b0 ;
wire                  cs1_rsv = ~ cs1_in;
wire                  cs2_rsv = ~ cs2_in;
wire			cmdrd_fu_out = ~mmc_enable;
wire			cmdrddatadone_fu_out = ~spimode;
wire			statuswr_fu_out = ~getstatus;
wire	[`BYTE:`LSB]	statuswrdata_fu_out = ~ cmdrddata_uf_in ;
wire			statuswrdatadone_fu_out = ~cmdrdready_uf_in;

wire			endp1rd_fu_out = ~endp1rdready_uf_in;
wire			endp1rddatadone_fu_out = ~ statuswrready_uf_in;

wire			endp2wr_fu_out = endp2wrready_uf_in;
wire	[`BYTE:`LSB]	endp2wrdata_fu_out = ~ endp1rddata_uf_in ;
wire			endp2wrdatadone_fu_out = ~datain_cmd_in;

wire			clock_fc_out = ~ dataout_dat_in ;
wire			datain_cmd_out = ~ disablebus;
wire			datain_cmd_enable = ~ getdata;

wire			dataout_dat_out = ~getdata ;

wire  			dataout_dat_enable = ( divide_rate == 0 ) ? 1: 0 ;

wire            clk_mcu = sof;
wire            busy_end_out  = data_in;
wire            data_out  = data_in;
gen_clock_5m u0_gen_clock_5m(
                              .usb_48_clock_uf_in(usb_48_clock_uf_in),
                              .usb_clock_uf_in(usb_clock_uf_in),
                              .divide_rate(divide_rate),
                              .sync_reset_uf_in(sync_reset_uf_in),
                              .sync_reset_made(sync_reset_made),
                              .clock_5m(clock_5m_out)
                             );


endmodule