ufiforxcont.v

实现USB接口功能的VHDL和verilog完整源代码

module Ufiforxcont (
		 setcmdwr,
		 getdata,
		 mcclock,
		 usbclock,
		 syncreset,
		 mmcreset,
		 fifowr,
		 fiford,
		 fifowraddr,
		 fifordaddr,
		 fifordready,
		 fifowrready,
		 datapacketok,
		 datapacketnotok
		 );
  input          mcclock;
  input			 usbclock;
  input			 syncreset;
  input          mmcreset;
  input			 fifowr;
  input			 fiford;
  input          getdata;
  input          setcmdwr;

  parameter		 DFFDEPTH = 32,
    			 DFFWIDTH = 8,
	    		 FULL = 8,
	    		 DFFADDRWIDTH = 5;	// 2^6 is 64
  
  output		 fifordready;
  output		 fifowrready;
  input			 datapacketok;
  input			 datapacketnotok;

  output[DFFADDRWIDTH-1:0] fifowraddr;
  output[DFFADDRWIDTH-1:0] fifordaddr;

  reg [DFFADDRWIDTH:0] wraddr,rdaddr,oldrdaddr;
  wire			 full,empty;
  
  wire[DFFADDRWIDTH-1:0] fifowraddr = wraddr[DFFADDRWIDTH-1:0];
  wire[DFFADDRWIDTH-1:0] fifordaddr = rdaddr[DFFADDRWIDTH-1:0];
  
  always @(posedge usbclock)
    begin
      if (syncreset || (!getdata && !setcmdwr) )
	begin
	  rdaddr <= 'h0;
	  oldrdaddr <= 'h0;
	end // if (syncreset)
      else
	begin
	  rdaddr <= (fiford) ? rdaddr + 1'b1 : (datapacketnotok) ?
	    oldrdaddr : rdaddr;
	  oldrdaddr <= (datapacketok) ? rdaddr : oldrdaddr;
	end // else: !if(syncreset)
    end // always @ (posedge usbclock)
 
 always@(posedge mcclock)
   begin
	if(mmcreset || (!getdata && !setcmdwr) )
	  wraddr <='h0;
    else
	  wraddr <= (fifowr) ? wraddr + 1'b1 : wraddr;
  end
  
  
  assign empty = oldrdaddr[DFFADDRWIDTH:0] == wraddr[DFFADDRWIDTH:0];
  assign full = (rdaddr[DFFADDRWIDTH-1:0] == wraddr[DFFADDRWIDTH-1:0]) &&
                (wraddr[DFFADDRWIDTH] != rdaddr[DFFADDRWIDTH]);
  
  //wire fifordready =  full;
  //wire fifowrready = ~full;
 reg fifordready;
 reg fifowrready;

always@(posedge usbclock)
     fifordready =  full ? 1: (empty ? 0: fifordready);

always@(posedge mcclock)
   fifowrready =  full ? 0 : (empty ? 1 : fifowrready);

//  wire fifowrready = ~fifordready ;

  // synopsys translate_off
  always @(posedge usbclock)
    begin
      if (full && fifowr && !fiford)
	$write ("Error :****** %m fifo overrun at time %t\n",$time);
      if (empty && ~fifowr && fiford)
	$write ("Error :****** %m fifo underrun at time %t\n",$time);
    end // always @ (posedge usbclock)

  // synopsys translate_on

endmodule