tb_transform.v

来自「Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。」· Verilog 代码 · 共 10 行

module tb_transform; 

wire clk, rst, sp, Ds;
wire [7:0] Dp;

test_signal test (clk, rst, sp, Ds, Dp);
transform transform (clk, rst, sp, Ds, Dp);
  
endmodule