xcv.v

来自「verilog编写的状态机检测00100序列. 实现 input:...011」· Verilog 代码 · 共 50 行

module xcv(x,z,clk,rst,state);
  input x,clk,rst;
 output z;
 output[2:0] state;
 reg[2:0] state;
 wire z;
 parameter IDIE='d0,A='d1,B='d2,C='d3,D='d4,E='d5;
 assign z=(state==E&&x==0)? 1:0;
 always @(posedge clk)
  if(!rst)
   begin
       state<=IDIE;
   end
  else
   case(state)
   IDIE:if(x==0)
        begin
        state<=A;
        end
    A:  if(x==0)
        begin
        state<=B;
        end
        else state<=IDIE;
    B:  if(x==1)
        begin
            state<=C;
        end
        else state<=B;
    C:  if(x==0)
        begin
            state<=D;
        end
        else state<=IDIE;
    D:  if(x==0)
        begin
          state<=E; 
        end
          else state<=A; 
    E:  if(x==0)
        begin
          state<=B; 
        end
        else state<=IDIE;
        
     default:state<=IDIE;
endcase
endmodule