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47译码器器的verilog源代码,经过编译仿真的

# Reading C:/Modeltech_xe/tcl/vsim/pref.tcl 
#  OpenFile "C:/Modeltech_xe/examples/qiangdaqi1/yimazhenque/dcb.v" 
# Loading project decode
# Compile of dcb.v was successful.
# Compile of dcbt_sest.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.decode47_test
# vsim work.decode47_test 
# Loading work.decode47_test
# Loading work.decode47
# ** Warning: (vsim-3009) [TSCALE] - Module 'decode47' does not have a `timescale directive in effect, but previous modules do.
#         Region: /decode47_test/decode47
add wave sim:/decode47_test/*
run -all
#                    0   
# bp_status  
# bp_status 0 1 C:/Modeltech_xe/examples/qiangdaqi1/yimazhenque/dcb.v 12 0 0