_primary.vhd

来自「47译码器器的verilog源代码,经过编译仿真的」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity decode47 is
    port(
        A               : out    vl_logic;
        B               : out    vl_logic;
        C               : out    vl_logic;
        D               : out    vl_logic;
        E               : out    vl_logic;
        F               : out    vl_logic;
        G               : out    vl_logic;
        D3              : in     vl_logic;
        D2              : in     vl_logic;
        D1              : in     vl_logic;
        D0              : in     vl_logic
    );
end decode47;