my_division.v

一个电子中的verilog实验源代码。适合verilog初学者学习参考

// **********************************************************************************
// FileName		: my_division.v
//
// Discription	:调用通用分频器,将30MHZ分频成1000Hz,100HZ,5HZ,1HZ
//
// Date			:
//
// Author		: dandan
// **********************************************************************************
//由于仿真需要，实际上是把30000分频改为30分频，这样就可以用1ms代替实际的1s

module my_division(glbclk,reset,clk_1000,clk_100,clk_5,clk_1);
input	glbclk,reset;
output	clk_1000,clk_100,clk_5,clk_1;

reg [15:0] half_f_1000,half_f_100,half_f_5,half_f_1;
reg clk_1,clk_5,clk_100,clk_1000;
wire clk_o1,clk_o2,clk_o3,clk_o4;
	always @ (posedge glbclk)		//30分频
	begin
		if (reset)
		begin
			half_f_1000 <= 15;		
			clk_1000 <= 1;
		end
		else
			clk_1000 <= clk_o4;
	end
	
	always @ (posedge glbclk)		//300分频
	begin
		if (reset)
		begin
			half_f_100 <= 150;		
			clk_100 <= 1;
		end
		else
			clk_100 <= clk_o1;
	end
	
	always @ (posedge glbclk)		//300*20分频
	begin
		if (reset)
		begin
			half_f_5 <= 3000;
			clk_5 <= 1;
		end
		else
			clk_5 <= clk_o2; 
	end
	
	always @ (posedge glbclk)		//300*100分频
	begin
		if (reset)
		begin
			half_f_1 <= 15000;		
			clk_1 <= 1;
		end
		else
			clk_1 <= clk_o3;
	end
	
	division div1(
					.reset(reset),
					.half_f_i(half_f_100),
					.clk_i(glbclk),
					.clk_o(clk_o1));
	division div2(
					.reset(reset),
					.half_f_i(half_f_5),
					.clk_i(glbclk),
					.clk_o(clk_o2));
	division div3(
					.reset(reset),
					.half_f_i(half_f_1),
					.clk_i(glbclk),
					.clk_o(clk_o3));
					
	division div4(
					.reset(reset),
					.half_f_i(half_f_1000),
					.clk_i(glbclk),
					.clk_o(clk_o4));
	
endmodule